Get started
Author

Jin‐Fa Lin

Observed names: J.-F. LIN, J.-F. Lin, Jin-Fa LIN, Jin-Fa Lin, Jin-fa Lin, Jin-fa lin, Jinfa Lin
ORCID: 0000-0001-6240-6055
Observed ORCID: 0000-0001-6240-6055
OpenAlex ID: A5000277158
A Novel High-Speed and Energy Efficient 10-Transistor Full Adder Design
2007 · Jin-Fa Lin, Yin-Tsung Hwang, et al. · IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications · 222
Tomato Disease Detection and Classification by Deep Learning
2020 · Huiqun Hong, Jinfa Lin, et al. · International Conference on Big Data, Artificial Intelligence and Internet of Things Engineering (ICBAIE) · 144
Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme
2011 · Yin-Tsung Hwang, Jin-Fa Lin, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 86
Low-Power 19-Transistor True Single-Phase Clocking Flip-Flop Design Based on Logic Structure Reduction Schemes
2017 · Jin-Fa Lin, Ming-Hwa Sheu, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 73
Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through
2013 · Jin-Fa Lin · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 62
Single‐ended structure sense‐amplifier‐based flip‐flop for low‐power systems
2014 · Jin‐Fa Lin, Yin‐Tsung Hwang, et al. · Electronics Letters · 31
PDF
Low Voltage and Low Power Divide-By-2/3 Counter Design Using Pass Transistor Logic Circuit Technique
2011 · Yin-Tsung Hwang, Jin-Fa Lin · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 31
Integrating BIM and IoT technology in environmental planning and protection of urban utility tunnel construction
2018 · Chih-ming Wu, Hsin-lung Liu, et al. · IEEE International Conference on Advanced Manufacturing (ICAM) · 24
Low power 10-transistor full adder design based on degenerate pass transistor logic
2012 · Jin-Fa Lin, Yin-Tsung Hwang, et al. · IEEE International Symposium on Circuits and Systems proceedings · 21
Novel Low-Complexity and Low-Power Flip-Flop Design
2020 · Jin-Fa Lin, Zheng-Jie Hong, et al. · Electronics · 11
PDF
Semantic Lung Segmentation Using Convolutional Neural Networks
2020 · Ching-Sheng Chang, Jin-Fa Lin, et al. · Informatik aktuell · 11
An Ultra-low-power True Single-phase Clocking Flip-flop with Improved Hold time Variation using Logic Structure Reduction Scheme
2018 · Ming-Yan Tsai, Po-Yu Kuo, et al. · IEEE International Symposium on Circuits and Systems proceedings · 11
Low-power pulse-triggered flip–flop design using gated pull-up control scheme
2011 · J.-F. Lin · Electronics Letters · 10
Low-Voltage and Low-Power True-Single-Phase 16-Transistor Flip-Flop Design
2022 · Jin-Fa Lin, Zheng-Jie Hong, et al. · Sensors · 8
PDF
Low Power Multipliers Using Enhenced Row Bypassing Schemes
2007 · Yin-Tsung Hwang, Jin-Fa Lin, et al. · SiPS ... design and implementation - IEEE Workshop on Signal Processing Systems · 8
Low Power Multiplier Designs Based on Improved Column Bypassing Schemes
2006 · Ying-Tsung Hwang, Jin-Fa Lin, et al. · IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) · 8
A Novel Cross-Latch Shift Register Scheme for Low Power Applications
2020 · Po-Yu Kuo, Ming-Hwa Sheu, et al. · Applied Sciences · 7
PDF
Novel Low Voltage and Low Power Array Multiplier Design for IoT Applications
2019 · Jin-Fa Lin, Cheng-Yu Chan, et al. · Electronics · 7
PDF
Stable Local Bit-Line 6 T SRAM Architecture Design for Low-Voltage Operation and Access Enhancement
2021 · Ming-Hwa Sheu, S M Salahuddin Morsalin, et al. · Electronics · 6
PDF
MVDR based adaptive beamformer design and its FPGA implementation for ultrasonic imaging
2016 · Shin-Shiang Wang, Yi-Chi Tien, et al. · IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) · 6
Safety Monitoring System of Stamping Presses Based on YOLOv8n Model
2025 · Tsoi-Na Fung, Yao-Hsuan Ku, et al. · IEEE Access · 5
A 0.3 V PNN Based 10T SRAM with Pulse Control Based Read-Assist and Write Data-Aware Schemes for Low Power Applications
2021 · Ming-Hwa Sheu, Chang-Ming Tsai, et al. · Sensors · 5
PDF
Low Power Latch-adder Based Multiplier Design
2017 · Jin-Fa Lin · JSTS Journal of Semiconductor Technology and Science · 4
Low Complexity Dual-Mode Pulse Generator Designs
2008 · J.-F. LIN, Y.-T. HWANG, et al. · IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences · 4
A novel low power flip-flop design using footless scheme
2018 · Jin-Fa Lin, Ming-Yan Tsai, et al. · Analog Integrated Circuits and Signal Processing · 3
Works count: 49
Citation count: 811
H-index: 11
I10-index: 12
Year
Topic
Type