Author

M. Stoutjesdijk

Observed institutions: NXP (Netherlands), Philips (Netherlands)

OpenAlex ID: A5000954209

A methodology to predict the impact of wafer level chip scale package stress on high-precision circuits

2015 · R. van Dalen, H. P. Tuinhout, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 12

Extended (180 V) voltage in 0.6 μm thin-layer-SOI A-BCD3 technology on 1 μm BOX for display, automotive and consumer applications

2003 · A.W. Ludikhuize, J.A. van der Pol, et al. · IEEE International Symposium on Power Semiconductor Devices and ICs/Proceedings of the International Symposium on Power Semiconductor Devices & ICs/Proceedings of the ... International Symposium on Power Semiconductor Devices & ICs/Proceedings of the ... International Symposium on Power Semiconductor Devices and ICs · 10

Thermal heating within SOI

2008 · J.J. Koning, S. Lecaudey, et al. · Microelectronics Reliability · 2

Wafer-specific centering of compact transistor model parameters for advanced technologies and models

2011 · B. De Vries, A.J. Scholten, et al. · IEEE Custom Integrated Circuits Conference (CICC)

Works count: 4

Citation count: 24

H-index: 2

I10-index: 2