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Hsing-Chung Liang

Observed names: H.-C. Liang, HSING-CHUNG LIANG, Hsin-Chung Liang
ORCID: 0000-0003-3378-9311
Observed ORCID: 0000-0003-3378-9311
OpenAlex ID: A5001019017
Machine Learning-Based Detection Method for Wafer Test Induced Defects
2021 · Ken Chau-Cheung Cheng, Leon Li-Yang Chen, et al. · IEEE Transactions on Semiconductor Manufacturing · 68
Identifying untestable faults in sequential circuits
1995 · Hsing-Chung Liang, Chung Len Lee, et al. · IEEE Design & Test of Computers · 39
Wafer Defect Pattern Labeling and Recognition Using Semi-Supervised Learning
2022 · Katherine Shu-Min Li, Xu-Hao Jiang, et al. · IEEE Transactions on Semiconductor Manufacturing · 34
Hidden Wafer Scratch Defects Projection for Diagnosis and Quality Enhancement
2020 · Katherine Shu-Min Li, Peter Yi-Yu Liao, et al. · IEEE Transactions on Semiconductor Manufacturing · 18
Invalid state identification for sequential circuit test generation
2002 · Hsing-Chung Liang, Chung Len Lee, et al. · Proceedings - Asian Test Symposium/Proceedings · 13
An effective methodology for mixed scan and reset design based on test generation and structure of sequential circuits
2003 · Hsing-Chung Liang, Chung Len Lee · Proceedings - Asian Test Symposium/Proceedings · 11
Identifying invalid states for sequential circuit test generation
1997 · Hsing-Chung Liang, Chung Len Lee, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 11
Wafer Scratch Pattern Reconstruction for High Diagnosis Accuracy and Yield Optimization
2022 · Katherine Shu-Min Li, Leon Li-Yang Chen, et al. · IEEE Transactions on Semiconductor Manufacturing · 10
Wafer-Level Test Path Pattern Recognition and Test Characteristics for Test-Induced Defect Diagnosis
2020 · Ken Chau-Cheung Cheng, Katherine Shu-Min Li, et al. · Design, Automation, and Test in Europe · 10
Bus-oriented DFT design for embedded cores
2005 · Chih-Yi Lin, Hsing-Chung Liang · IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) · 9
Semi-Supervised Framework for Wafer Defect Pattern Recognition with Enhanced Labeling
2021 · Leon Li-Yang Chen, Katherine Shu-Min Li, et al. · IEEE International Test Conference (ITC) · 8
Testing transition delay faults in modified Booth multipliers by using C-testable and SIC patterns
2007 · Hsing-Chung Liang, Pao-Hsin Huang · IEEE Region 10 Conference (TENCON) · 6
A sequential redundant fault identification scheme and its application to test generation
2002 · Hsing-Chung Liang, Chung Len Lee, et al. · Proceedings - Asian Test Symposium/Proceedings · 6
Partial reset and scan for flip-flops based on states requirement for test generation
2002 · Hsing-Chung Liang, Chung Len Lee, et al. · IEEE VLSI Test Symposium (VTS) · 6
Testing Transition Delay Faults in Modified Booth Multipliers
2008 · Hsing-Chung Liang, Pao-Hsin Huang, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 5
Identify Unrepairability to Speed-Up Spare Allocation for Repairing Memories
2005 · H.-C. Liang, W.-C. Ho, et al. · IEEE Transactions on Reliability · 4
Automatic Inspection for Wafer Defect Pattern Recognition with Unsupervised Clustering
2021 · Katherine Shu-Min Li, Leon Li-Yang Chen, et al. · IEEE European Test Symposium (ETS) · 3
Multi-function controller for low-power multiple scan test of transition delay faults
2014 · Hsing-Chung Liang, Chang-Jung Ho · International Symposium on Next-Generation Electronics · 2
High and low speed output buffer design with reduced switching noise for USB applications
2005 · Hwang‐Cherng Chow, C.I. Huang, et al. · International Conference on Circuits · 1
Development of a readout circuit and platform for uric acid measurement for urolithiasis application
2026 · Meo Vincent Caya, Wen-Yaw Chung, et al. · Frontiers in Bioengineering and Biotechnology
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GPU-based ATPG System by Scaling Memory Usage and Reducing Data Transfer
2021 · Hua-Ren Li, Hsing-Chung Liang · IEEE European Test Symposium (ETS)
Improved Representatives for Judging Unrepairability and Deciding Economic Repair Solutions of Memories
2009 · HSING-CHUNG LIANG · Journal of Circuits Systems and Computers
Improved Representatives for Unrepairability Judging and Economic Repair Solutions of Memories
2006 · Hsing-Chung Liang, Le-Quen Tzeng · Records of the IEEE International Workshop on Memory Technology, Design, and Testing
Novel frequency doubler circuits and dividers using duty cycle control buffers
2005 · Hwang‐Cherng Chow, Hsing-Chung Liang · International Conference on Circuits
Speed-up of memory failure shape analysis
2005 · Jyh-Ming Jang, Hsing-Chung Liang, et al. · International Conference on Circuits
Works count: 26
Citation count: 264
H-index: 9
I10-index: 9
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