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K. Gavaskar

Observed names: Gavaskar K, Gavaskar K., Gavaskar Kanagara, K Gavaskar
ORCID: 0000-0003-4432-339X
Observed ORCID: 0000-0003-4432-339X
OpenAlex ID: A5002391367
Implementation of Sobel operator based image edge detection on FPGA
2020 · G. Ravivarma, K. Gavaskar, et al. · Materials Today Proceedings · 61
Low power self-controllable voltage level and low swing logic based 11T SRAM cell for high speed CMOS circuits
2018 · K. Gavaskar, U. S. Ragupathy · Analog Integrated Circuits and Signal Processing · 41
Design of Novel SRAM Cell Using Hybrid VLSI Techniques for Low Leakage and High Speed in Embedded Memories
2019 · K. Gavaskar, U. S. Ragupathy, et al. · Wireless Personal Communications · 30
Functional verification environment for I2C master controller using system verilog
2017 · M. Sukhanya, K. Gavaskar · International Conference on Signal Processing, Communication and Networking (ICSCN) · 24
A novel design and implementation of IoT based real-time ATM surveillance and security system
2021 · K. Gavaskar, U. S. Ragupathy, et al. · Advances in Computational Intelligence · 18
An efficient design and comparative analysis of low power memory cell structures
2014 · K. Gavaskar, U. S. Ragupathy · International Conference on Green Computing Communication and Electrical Engineering · 15
A Comprehensive Survey on Detection of Ocular and Non-Ocular Diseases Using Color Fundus Images
2024 · Megha Gupta, Sneha Gupta, et al. · IEEE Access · 14
Design of Efficient Low Power Stable 4-Bit Memory Cell
2013 · K. Gavaskar, S. Priya · International Journal of Computer Applications · 14
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Design and comparative analysis of SRAM array using low leakage controlled transistor technique with improved delay
2021 · K. Gavaskar, M. Sankara Narayanan, et al. · Journal of Ambient Intelligence and Humanized Computing · 13
Low-Power SRAM Cell and Array Structure in Aerospace Applications: Single-Event Upset Impact Analysis
2022 · K. Gavaskar, P. Sivaranjani, et al. · Wireless Personal Communications · 12
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Development of LPG Leakage Detection Alert and Auto Exhaust System using IoT
2021 · K Gavaskar, D Malathi, et al. · International Conference on Electrical Energy Systems (ICEES) · 12
Proposed Design of 1 KB Memory Array Structure for Cache Memories
2019 · K. Gavaskar, U. S. Ragupathy, et al. · Wireless Personal Communications · 12
Low Power CMOS Design of Phase Locked Loop for Fastest Frequency Acquisition at Various Nanometer Technologies
2022 · K. Gavaskar, R. Dhivya, et al. · Wireless Personal Communications · 11
A Fresh Design of Power Effective Adapted Vedic Multiplier for Modern Digital Signal Processors
2021 · K. Gavaskar, D. Malathi, et al. · Wireless Personal Communications · 10
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Low Power Design of 4-bit Simultaneous Counter using Digital Switching Circuits for Low Range Counting Applications
2020 · K. Gavaskar, D. Malathi, et al. · International Conference on Devices, Circuits and Systems (ICDCS) · 10
Design of Low Power Multiplier with Less Area Using Quaternary Carry Increment Adder for New-Fangled Processors
2022 · K. Gavaskar, D. Malathi, et al. · Wireless Personal Communications · 8
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Design and Analysis of 8-Bit Stable SRAM for Ultra Low Power Applications
2020 · K. Gavaskar, G. Ravivarma, et al. · International Conference on Devices, Circuits and Systems (ICDCS) · 8
An Efficient Design and Analysis of Low Power SRAM Memory Cell for Ultra Applications
2017 · K. Gavaskar, U. S. Ragupathy · Asian Journal of Research in Social Sciences and Humanities · 8
Design Of Efficient Low Power 9t Sram Cell
2013 · K. Gavaskar, S. Priya · 7
New approach for improving the performance of dual axis solar tracker with auto cleaning system
2023 · K. Gavaskar, U. S. Ragupathy · Soft Computing · 6
A low-power, full-custom design of a 4:2 compressor using 32 nm CNTFET technology for high-speed signal processing
2025 · K. Gavaskar, S. Elango, et al. · Analog Integrated Circuits and Signal Processing · 5
Design of Reconfigurable Signed Dual Modulo Multiplier Function (DMMF) for RNS
2021 · Elango Sekar, Sampath Palaniswami, et al. · International Conference on Smart Technologies, Communication and Robotics (STCR) · 3
Design of Novel SRAM cell using Hybrid VLSI Techniques for Low Power and High Speed in Embedded Memories
2018 · K. Gavaskar, U.S. Ragupathy, et al. · International Conference on Intelligent Computing and Communication for Smart World (I2C2SW) · 3
Design and verification of LTSSM in USB 3.0 link layer using system verilog
2017 · M. Sukhanya, T. Chandra Kumar, et al. · International Conference on Signal Processing, Communication and Networking (ICSCN) · 3
Design of Barrel Shift Registers with Enhanced Performance Analysis for Modern Processors
2025 · K. Gavaskar, K. Paramasivam, et al. · International Conference on Advancements in Electrical, Electronics, Communication, Computing and Automation (ICAECA) · 2
Works count: 48
Citation count: 361
H-index: 12
I10-index: 15
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