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Basavaraj Talawar

Observed names: Basavaraj Talwar, Talawar, Basavaraj
ORCID: 0000-0001-5054-3124
Observed ORCID: 0000-0001-5054-3124
OpenAlex ID: A5004440264
Machine Learning Based Framework to Predict Performance Evaluation of On-Chip Networks
2018 · Anil Kumar, Basavaraj Talawar · International Conference on Contemporary Computing · 29
Parallel Version of Local Search Heuristic Algorithm to Solve Capacitated Vehicle Routing Problem
2021 · Pramod Yelmewad, Basavaraj Talawar · Cluster Computing · 16
Power and performance analysis of 3D network-on-chip architectures
2020 · Bheemappa Halavar, Basavaraj Talawar · Computers & Electrical Engineering · 15
Traffic engineered NoC for streaming applications
2013 · Basavaraj Talwar, Bharadwaj Amrutur · Microprocessors and Microsystems · 14
A Detailed Study of SOT-MRAM as an Alternative to DRAM Primary Memory in Multi-Core Environment
2024 · H. D. Kallinatha, Sadhana Rai, et al. · IEEE Access · 11
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YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine Using FPGAs
2018 · Prabhu Prasad B M, Khyamling Parane, et al. · International Conference on VLSI Design and International Conference on Embedded Systems (VLSID) · 10
On the Cache Behavior of SPLASH-2 Benchmarks on ARM and ALPHA Processors in Gem5 Full System Simulator
2014 · B. Vikas, Basavaraj Talawar · International Conference on Eco-friendly Computing and Communication Systems (ICECCS) · 10
An Efficient FPGA-Based Network-on-Chip Simulation Framework Utilizing the Hard Blocks
2020 · B. M. Prabhu Prasad, Khyamling Parane, et al. · Circuits Systems and Signal Processing · 9
GPU implementation of non-local maximum likelihood estimation method for denoising magnetic resonance images
2016 · Adithya H. K. Upadhya, Basavaraj Talawar, et al. · Journal of Real-Time Image Processing · 9
FPGA friendly NoC simulation acceleration framework employing the hard blocks
2021 · B. M. Prabhu Prasad, Khyamling Parane, et al. · Computing · 7
LBNoC
2020 · Khyamling Parane, Prabhu Prasad B M, et al. · ACM Transactions on Design Automation of Electronic Systems · 7
Parallel iterative hill climbing algorithm to solve TSP on GPU
2018 · Pramod Yelmewad, Basavaraj Talawar · Concurrency and Computation Practice and Experience · 7
Design of an Adaptive and Reliable Network on Chip Router Architecture Using FPGA
2019 · Khyamling Parane, B. M Prabhu Prasad, et al. · International Symposium on VLSI Design, Automation and Test · 6
Latency, Power and Performance Trade-Offs in Network-on-Chips by Link Microarchitecture Exploration
2009 · Basavaraj Talwar, Shailesh Kulkarni, et al. · International Conference on VLSI Design · 6
A Method for Resource and Service Discovery in MANETs
2006 · Basavaraj Talwar, Pallapa Venkataram, et al. · Wireless Personal Communications · 6
A Support Vector Regression-Based Approach to Predict the Performance of 2D & 3D On-Chip Communication Architectures
2019 · Anil Kumar, Basavaraj Talawar · International Conference on Smart Systems and Inventive Technology (ICSSIT) · 5
Extending BookSim2.0 and HotSpot6.0 for power, performance and thermal evaluation of 3D NoC architectures
2019 · Bheemappa Halavar, Ujjwal Pasupulety, et al. · Simulation Modelling Practice and Theory · 5
Nonvolatile Memory Technologies: Characteristics, Deployment, and Research Challenges
2023 · Sadhana Rai, Basavaraj Talawar · Springer eBooks · 4
Challenges in Design, Data Placement, Migration and Power-Performance Trade-offs in DRAM-NVM-based Hybrid Memory Systems
2022 · Sadhana Rai, Basavaraj Talawar · IETE Technical Review · 4
LBF-NoC: Learning-Based Framework to Predict Performance, Power and Area for Network-On-Chip Architectures
2022 · Anil Kumar, Basavaraj Talawar · Journal of Circuits Systems and Computers · 4
Storage Class Memory: Principles, Problems, and Possibilities
2019 · Kamath, Aditya K, Monis, Leslie, et al. · arXiv (Cornell University) · 4
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High-Performance NoC Simulation Acceleration Framework Employing the Xilinx DSP48E1 Blocks
2019 · B M Prabhu Prasad, Khyamling Parane, et al. · International Symposium on VLSI Design, Automation and Test · 4
High-Performance NoCs Employing the DSP48E1 Blocks of the Xilinx FPGAs
2019 · Prabhu Prasad B.M., Khyamling Parane, et al. · International Symposium on Quality Electronic Design (ISQED) · 4
A Crossbar Interconnection Network in DNA
2015 · Basavaraj Talawar · 4
Parallel deterministic local search heuristic for minimum latency problem
2020 · Pramod Yelmewad, Basavaraj Talawar · Cluster Computing · 3
Works count: 61
Citation count: 247
H-index: 9
I10-index: 7
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