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Giuseppe Tagliavini
Observed name:
Tagliavini, Giuseppe
Institution:
University of Bologna
Observed institution:
University of Bologna
ORCID:
0000-0002-9221-4633
Observed ORCID:
0000-0002-9221-4633
OpenAlex ID:
A5004842257
Mr.Wolf: An Energy-Precision Scalable Parallel Ultra Low Power SoC for IoT Edge Processing
2019
·
Antonio Pullini
, Davide Rossi
, et al.
·
IEEE Journal of Solid-State Circuits
·
168
PDF
PULP: A parallel ultra low power platform for next generation IoT applications
2015
·
Davide Rossi
, Francesco Conti
, et al.
·
IEEE Hot Chips Symposium
·
121
Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode
2021
·
Davide Rossi
, Francesco Conti
, et al.
·
IEEE Journal of Solid-State Circuits
·
119
PDF
A transprecision floating-point platform for ultra-low power computing
2018
·
Giuseppe Tagliavini
, Stefan Mach
, et al.
·
Design, Automation, and Test in Europe
·
116
XpulpNN: Accelerating Quantized Neural Networks on RISC-V Processors Through ISA Extensions
2020
·
Angelo Garofalo
, Giuseppe Tagliavini
, et al.
·
Design, Automation, and Test in Europe
·
85
PDF
The transprecision computing paradigm: Concept, design, and applications
2018
·
A. Cristiano I. Malossi
, Michael Schaffner
, et al.
·
Design, Automation, and Test in Europe
·
84
PDF
GVSoC: A Highly Configurable, Fast and Accurate Full-Platform Simulator for RISC-V based IoT Processors
2021
·
Nazareno Bruschi
, Germain Haugou
, et al.
·
IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD)
·
57
PDF
XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Networks on RISC-V Based IoT End Nodes
2021
·
Angelo Garofalo
, Giuseppe Tagliavini
, et al.
·
IEEE Transactions on Emerging Topics in Computing
·
57
PDF
4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode
2021
·
Davide Rossi
, Francesco Conti
, et al.
·
Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
·
54
BioWolf: A Sub-10-mW 8-Channel Advanced Brain–Computer Interface Platform With a Nine-Core Processor and BLE Connectivity
2019
·
Victor Kartsch
, Giuseppe Tagliavini
, et al.
·
IEEE Transactions on Biomedical Circuits and Systems
·
51
A Mixed-Precision RISC-V Processor for Extreme-Edge DNN Inference
2020
·
Gianmarco Ottavi
, Angelo Garofalo
, et al.
·
IEEE Computer Society Annual Symposium on VLSI
·
49
PDF
DNN Is Not All You Need: Parallelizing Non-neural ML Algorithms on Ultra-low-power IoT Processors
2023
·
Enrico Tabanelli
, Giuseppe Tagliavini
, et al.
·
ACM Transactions on Embedded Computing Systems
·
48
PDF
A Transprecision Floating-Point Architecture for Energy-Efficient Embedded Computing
2018
·
Stefan Mach
, Davide Rossi
, et al.
·
IEEE International Symposium on Circuits and Systems proceedings
·
40
PDF
FlexFloat: A Software Library for Transprecision Computing
2018
·
Giuseppe Tagliavini
, Andrea Marongiu
, et al.
·
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
·
39
Towards Long-term Non-invasive Monitoring for Epilepsy via Wearable EEG Devices
2021
·
Thorir Mar Ingolfsson
, Andrea Cossettini
, et al.
·
IEEE Biomedical Circuits and Systems Conference (BioCAS)
·
37
PDF
Unleashing Fine-Grained Parallelism on Embedded Many-Core Accelerators with Lightweight OpenMP Tasking
2018
·
Giuseppe Tagliavini
, Daniele Cesarini
, et al.
·
IEEE Transactions on Parallel and Distributed Systems
·
37
PDF
Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster With 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode
2023
·
Gianmarco Ottavi
, Angelo Garofalo
, et al.
·
IEEE Transactions on Circuits and Systems I Regular Papers
·
34
PDF
Design and Evaluation of SmallFloat SIMD extensions to the RISC-V ISA
2019
·
Giuseppe Tagliavini
, Stefan Mach
, et al.
·
Design, Automation, and Test in Europe
·
29
PDF
Energy efficient parallel computing on the PULP platform with support for OpenMP
2014
·
Davide Rossi
, Igor Loi
, et al.
·
IEEE Convention of Electrical and Electronics Engineers in Israel
·
27
PULP-TrainLib: Enabling On-Device Training for RISC-V Multi-core MCUs Through Performance-Driven Autotuning
2022
·
Davide Nadalini
, Manuele Rusci
, et al.
·
Lecture notes in computer science
·
26
PDF
Exploring architectural heterogeneity in intelligent vision systems
2015
·
Nanchini Chandramoorthy
, Giuseppe Tagliavini
, et al.
·
IEEE International Symposium on High-Performance Computer Architecture (HPCA)
·
26
Optimizing Random Forest-Based Inference on RISC-V MCUs at the Extreme Edge
2022
·
Enrico Tabanelli
, Giuseppe Tagliavini
, et al.
·
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
·
25
PDF
A Low-Power Transprecision Floating-Point Cluster for Efficient Near-Sensor Data Analytics
2021
·
Fabio Montagna
, Stefan Mach
, et al.
·
IEEE Transactions on Parallel and Distributed Systems
·
25
PDF
TRANSPIRE: An energy-efficient TRANSprecision floating-point Programmable archItectuRE
2020
·
Rohit Prasad
, Satyajit Das
, et al.
·
Design, Automation, and Test in Europe
·
24
PDF
Improving the programmability of STHORM-based heterogeneous systems with offload-enabled OpenMP
2013
·
Andrea Marongiu
, Alessandro Capotondi
, et al.
·
23
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Works count:
80
Citation count:
1,682
H-index:
24
I10-index:
37
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