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Author

Hugues Cassé

Observed names: CASSE, Hugues, Cassé Hugues, Cassé, Hugues, H. Casse, H. Cassé, Hugues Casse, Hugues Cassé, Hugues Cassé A
Observed institutions: Centre National de la Recherche Scientifique, Université Toulouse III - Paul Sabatier, University of Augsburg, Institut National Polytechnique de Toulouse, Office National d'Études et de Recherches Aérospatiales, Institut de Recherche en Informatique de Toulouse, Université Toulouse - Jean Jaurès, Université de Toulouse
ORCID: 0000-0002-9298-5235
Observed ORCID: 0000-0002-9298-5235
OpenAlex ID: A5006018472
OTAWA: An Open Toolbox for Adaptive WCET Analysis
2010 · Clément Ballabriga, Hugues Cassé, et al. · Lecture notes in computer science · 210
Merasa: Multicore Execution of Hard Real-Time Applications Supporting Analyzability
2010 · Theo Ungerer, Francisco Cazorla, et al. · IEEE Micro · 178
PapaBench: a Free Real-Time Benchmark
2006 · Nemer, Fadia, Cassé, Hugues, et al. · DROPS (Schloss Dagstuhl – Leibniz Center for Informatics) · 114
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Static Loop Bound Analysis of C Programs Based on Flow Analysis and Abstract Interpretation
2008 · Marianne de Michiel, Armelle Bonenfant, et al. · IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA) · 63
parMERASA -- Multi-core Execution of Parallelised Hard Real-Time Applications Supporting Analysability
2013 · T. Ungerer, C. Bradatsch, et al. · Euromicro Conference on Digital System Design (DSD) · 60
Deterministic Execution Model on COTS Hardware
2012 · Frédéric Boniol, Hugues Cassé, et al. · Lecture notes in computer science · 56
Improving the First-Miss Computation in Set-Associative Instruction Caches
2008 · Clément Ballabriga, Hugues Casse · Euromicro Conference on Real-Time Systems (ECRTS) · 42
RTOS Support for Parallel Execution of Hard Real-Time Applications on the MERASA Multi-core Processor
2010 · Julian Wolf, Mike Gerdes, et al. · IEEE International Symposium on Real-Time Distributed Computing (ISORC) · 37
OTAWA, a Framework for Experimenting WCET Computations
2006 · Cassé, Hugues, Sainrat, Pascal · HAL · 31
Parallelizing Industrial Hard Real-Time Applications for the parMERASA Multicore
2016 · Theo Ungerer, Christian Bradatsch, et al. · ACM Transactions on Embedded Computing Systems · 30
Speculative Execution and Timing Predictability in an Open Source RISC-V Core
2021 · Alban Gruin, Thomas Carle, et al. · IEEE Real-Time Systems Symposium (RTSS) · 21
WCET Tool Challenge 2011 : Report
2011 · Von Hanxleden, Reinhard, Holsti, Niklas, et al. · University of Hertfordshire Research Archive (University of Hertfordshire) · 21
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Accurate analysis of memory latencies for WCET estimation
2008 · Roman Bourgade, Clément Ballabriga, et al. · HAL · 20
FFX: a portable WCET annotation language
2012 · Armelle Bonenfant, Hugues Cassé, et al. · International Conference on Real-Time Networks and Systems (RTNS) · 13
MINOTAuR: A Timing Predictable RISC-V Core Featuring Speculative Execution
2022 · Alban Gruin, Thomas Carle, et al. · IEEE Transactions on Computers · 12
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Using SMT Solving for the Lookup of Infeasible Paths in Binary Programs
2015 · Ruiz, Jordy, Cassé, Hugues · DROPS (Schloss Dagstuhl – Leibniz Center for Informatics) · 11
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Inter-task WCET computation for a-way instruction caches
2008 · Fadia Nemer, Hugues Casse, et al. · IEEE International Symposium on Industrial Embedded Systems (SIES) · 11
WCET 2008 -- Report from the Tool Challenge 2008 -- 8th Intl. Workshop on Worst-Case Execution Time (WCET) Analysis
2008 · Holsti, Niklas, Gustafsson, Jan, et al. · DROPS (Schloss Dagstuhl – Leibniz Center for Informatics) · 11
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Wcet Tool Challenge 2008: Report
2008 · Niklas Holsti, Jan Gustafsson, et al. · 11
Improving the Performance of WCET Analysis in the Presence of Variable Latencies
2020 · Zhenyu Bai, Hugues Cassé, et al. · 10
Reducing Timing Interferences in Real-Time Applications Running on Multicore Architectures
2018 · Carle, Thomas, Cassé, Hugues · DROPS (Schloss Dagstuhl – Leibniz Center for Informatics) · 10
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A versatile generator of instruction set simulators and disassemblers
2009 · Tahiry Ratsiambahotra, Hugues Cassé, et al. · International Symposium on Performance Evaluation of Computer and Telecommunication Systems · 10
Static Extraction of Memory Access Profiles for Multi-core Interference Analysis of Real-Time Tasks
2021 · Thomas Carle, Hugues Cassé · Lecture notes in computer science · 9
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An improved approach for set-associative instruction cache partial analysis
2008 · C. Ballabriga, H. Casse, et al. · ACM Symposium on Applied Computing · 9
Computing Execution Times With Execution Decision Diagrams in the Presence of Out-of-Order Resources
2023 · Zhenyu Bai, Hugues Cassé, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 8
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Works count: 80
Citation count: 1,104
H-index: 13
I10-index: 22
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