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Mike Ignatowski
Observed name:
M. Ignatowski
Institution:
Advanced Micro Devices (United States)
Observed institutions:
Advanced Micro Devices (Canada),
IBM (United States),
IBM Research - Thomas J. Watson Research Center,
Advanced Micro Devices (United States)
ORCID:
0009-0009-7091-6982
Observed ORCID:
0009-0009-7091-6982
OpenAlex ID:
A5006421293
Heterogeneous memory architectures: A HW/SW approach for mixing die-stacked and off-package memories
2015
·
Mitesh R. Meswani
, Sergey Blagodurov
, et al.
·
IEEE International Symposium on High-Performance Computer Architecture (HPCA)
·
168
Interconnects in the Third Dimension: Design Challenges for 3D ICs
2007
·
Kerry Bernstein
, Paul Andry
, et al.
·
ACM/IEEE Design Automation Conference (DAC)
·
137
Achieving Exascale Capabilities through Heterogeneous Computing
2015
·
Michael J. Schulte
, Mike Ignatowski
, et al.
·
IEEE Micro
·
90
Design and Analysis of an APU for Exascale Computing
2017
·
Thiruvengadam Vijayaraghavan
, Arun Karunanithi
, et al.
·
IEEE International Symposium on High-Performance Computer Architecture (HPCA)
·
75
Realizing the AMD Exascale Heterogeneous Processor Vision : Industry Product
2024
·
Alan Smith
, Gabriel H. Loh
, et al.
·
Proceedings - International Symposium on Computer Architecture/Proceedings
·
56
A new perspective on processing-in-memory architecture design
2013
·
Dong Ping Zhang
, Nuwan Jayasena
, et al.
·
Workshop on Memory System Performance and Correctness
·
42
Analytical analysis of finite cache penalty and cycles per instruction of a multiprocessor memory hierarchy using miss rates and queuing theory
2001
·
R. E. Matick
, T. J. Heller
, et al.
·
IBM Journal of Research and Development
·
29
Co-ML: a case for Co llaborative ML acceleration using near-data processing
2019
·
Shaizeen Aga
, Nuwan Jayasena
, et al.
·
International Symposium on Memory Systems (MEMSYS)
·
25
Toward Efficient Programmer-Managed Two-Level Memory Hierarchies in Exascale Computers
2014
·
Mitesh R. Meswani
, Gabriel H. Loh
, et al.
·
21
Processing-in-Memory: Exploring the Design Space
2015
·
Marko Scrbak
, Mahzabeen Islam
, et al.
·
Lecture notes in computer science
·
19
Improving Node-Level MapReduce Performance Using Processing-in-Memory Technologies
2014
·
Mahzabeen Islam
, Marko Scrbak
, et al.
·
Lecture notes in computer science
·
17
Exploring the Processing-in-Memory design space
2016
·
Marko Scrbak
, Mahzabeen Islam
, et al.
·
Journal of Systems Architecture
·
16
A Research Retrospective on AMD's Exascale Computing Journey
2023
·
Gabriel H. Loh
, Michael J. Schulte
, et al.
·
Proceedings - International Symposium on Computer Architecture/Proceedings
·
13
PDF
Memory organizations for 3D-DRAMs and PCMs in processor memory hierarchy
2015
·
Krishna Kavi
, Stefano Pianelli
, et al.
·
Journal of Systems Architecture
·
9
New Memory Organizations for 3D DRAM and PCMs
2012
·
Ademola Fawibe
, Jared Sherman
, et al.
·
Lecture notes in computer science
·
7
Unified Deep Learning with CPU, GPU, and FPGA Technologies
2017
·
Allen Rush
, Ashish Sirasao
, et al.
·
5
3D DRAM and PCMs in Processor Memory Hierarchy
2014
·
Krishna Kavi
, Stefano Pianelli
, et al.
·
Lecture notes in computer science
·
3
Technology, CAD tools, and designs for emerging 3D integration technology
2008
·
Syed M. Alam
, Mike Ignatowski
, et al.
·
ACM Great Lakes Symposium on VLSI (GLSVLSI)
·
3
A Multi-core Memory Organization for 3-D DRAM as Main Memory
2013
·
Jared Sherman
, Krishna Kavi
, et al.
·
Lecture notes in computer science
·
2
Proposing an Abstracted Interface and Protocol for Computer Systems
2014
·
David Resnick
, Mike Ignatowski
·
OSTI OAI (U.S. Department of Energy Office of Scientific and Technical Information)
·
1
PDF
近データ処理を用いた協調ML加速のためのCo-ML【JST・京大機械翻訳】
2019
·
Aga Shaizeen
, Jayasena Nuwan
, et al.
·
ACM Proceedings
処理におけるメモリ設計空間の探索【Powered by NICT】
2017
·
Scrbak Marko
, Islam Mahzabeen
, et al.
·
Journal of Systems Architecture
Proposing an Abstracted Interface and Protocol for Computer Systems
2014
·
David Resnick
, Mike Ignatowski
·
OSTI OAI (U.S. Department of Energy Office of Scientific and Technical Information)
PDF
A Multi-core Memory Organization for 3D DRAM as Main Memory
2013
·
Jared Sherman
, Krishna Kavi
, et al.
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Works count:
25
Citation count:
738
H-index:
13
I10-index:
13
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