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Takeya Hirose
Institution:
Semiconductor Energy Laboratory (Japan)
Observed institution:
Semiconductor Energy Laboratory (Japan)
ORCID:
0009-0000-7599-6453
Observed ORCID:
0009-0000-7599-6453
OpenAlex ID:
A5006597113
1-Mbit 3-D DRAM Using a Monolithically Stacked Structure of a Si CMOS and Heterogeneous IGZO FETs
2024
·
Takeya Hirose
, Yuki Okamoto
, et al.
·
IEEE Journal of the Electron Devices Society
·
13
PDF
Heterogeneous Oxide Semiconductor FETs Comprising Planar FET and Vertical Channel FETs Monolithically Stacked on Si CMOS, Enabling 1-Mbit 3D DRAM
2024
·
Hiroki Inoue
, Takeya Hirose
, et al.
·
IEEE International Memory Workshop (IMW)
·
6
23‐2: 2351‐ppi OLED Display with Stacked OS‐FETs with L = 0.36 µm
2019
·
Hideaki Shishido
, Kiyotaka Kimura
, et al.
·
SID Symposium Digest of Technical Papers
·
5
28‐4: 1.50‐Inch, 3207‐ppi OLED Display and Optical System for VR Use
2023
·
Hisao Ikeda
, Ryo Hatsumi
, et al.
·
SID Symposium Digest of Technical Papers
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Works count:
4
Citation count:
24
H-index:
3
I10-index:
1
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