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Bhavesh Soni

Observed names: B Soni, Bhavesh H Soni, Bhavesh Soni*, Prof. Bhavesh Soni
Institution: Ganpat University
ORCID: 0000-0002-6482-9817
Observed ORCID: 0000-0002-6482-9817
OpenAlex ID: A5006676997
Design & Implementation of Novel Asynchronous FIFO
2023 · Vijay Patel, Vimal Mer, et al. · IEEE International Symposium on Smart Electronic Systems (iSES) · 7
Congestion Estimation Using Various Floorplan Techniques in 28nm Soc Design
2020 · Ashvi Soni, Bhavesh Soni, et al. · International Conference on Intelligent Computing and Control Systems (ICICCS) · 6
Optimization of Floorplan Strategies to Reduce Timing Violation on 28nm ASIC and Scopes of Improvement for Data Center ASICs
2020 · MohammedTareeq Shaikh, Bhavesh Soni, et al. · International Conference on Intelligent Computing and Control Systems (ICICCS) · 5
Integration of MODBUS/TCP master monitoring and control system using python for high power RF system
2015 · Krupa Mehta, Ramesh Joshi, et al. · International Conference on Electrical, Electronics, Signals, Communication and Optimization · 5
Performance Evaluation of 14-nm FinFET-Based Ring Counter Using BSIM-CMG Model
2017 · Bhavesh Soni, Gaurav Aryan, et al. · Lecture notes in networks and systems · 3
Design and Optimization in SPI Master at the RTL Level
2024 · Rajat R. Sahu, Mitur Patel, et al. · Communications in computer and information science · 2
Power Budget Improvement Using Floorplan Methodologies In Lower(28nm) Technology Node
2023 · Vidhi Gandhi, Yashvi Patel, et al. · IEEE International Symposium on Smart Electronic Systems (iSES) · 2
Performance Enhancement of “ARP Block” using 28nm Technology node
2023 · Vishal Mahida, Bhavesh Soni, et al. · IEEE International Symposium on Smart Electronic Systems (iSES) · 2
A Research Paper On The Electrical And Physical Characteristics Of FinFET Using LTspice
2023 · Nachiket Patel, Bhavesh Soni · IEEE Region Humanitarian Technology Conference · 2
Test Logic Insertion for Optimization of Testing Parameters on Lower Technology Node
2020 · Jhanvi Ravi Sheth, Bhavesh Soni, et al. · International Conference on Intelligent Computing and Control Systems (ICICCS) · 2
Practical Analysis of Various Approaches for Targeting Delay Faults at Functional Frequency in Automatic Test Pattern Generation (ATPG)
2023 · Bhavesh Soni, Kishor Purohit, et al. · IEEE International Symposium on Smart Electronic Systems (iSES) · 1
DFM Challenges and Solutions for 14nm FinFET
2015 · Ravi Dhanani, Bhavesh Soni · Communications on Applied Electronics · 1
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Architectural Integration of Specialized Low-Power Cells and UPF Constraints in Nanoscale VLSI Design
2026 · Rutvik Jesani, Harsh Chuhan, et al. · Indian Journal of VLSI Design
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Functional Verification of a 10G Ethernet MAC Using a UVM-Based VIP with Error Injection and Coverage Analysis
2026 · Tikesh Prajapati, Udit K Gohil, et al. · International Conference on Intelligent Technologies (CONIT)
Fault Injection and Out-of-Bound Access Detection in the SPI Protocol Using UVM
2026 · Tikesh Prajapati, Udit K Gohil, et al. · International Conference on Intelligent Technologies (CONIT)
Implementation-Aware UPF Methodology for Managing Power Domain Crossings in Multi-Voltage SoCs
2026 · Aayush Gade, Prof. Bhavesh Soni, et al. · Indian Journal of VLSI Design
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Three-Transistor Antifuse OTP Memory: Design, Simulation and Behavioral Verification
2026 · Jyoti Thakur, Prof. Bhavesh Soni · Indian Journal of VLSI Design
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Design, Implementation and Verification of UART with APB Slave Interface Using Verilog
2026 · Govindchandra Patel, Rahul Gandhi, et al. · Communications in computer and information science
Development and UVM-Based Functional Verification of a Scalable and Configurable UART VIP
2026 · Kinjal Patel, Bablu R. S. Mallick, et al. · Communications in computer and information science
Low-Power Logarithmic Amplifier with First-Stage Feedback for Digital Hearing Aid Applications: Design and Simulation
2025 · Prit Hansaliya, Vidhi Gandhi, et al. · International Conference for Advancement in Technology (ICONAT)
Enhancing ASIC Design Efficiency: A Focus on RTL Verification with Spyglass
2024 · Dhaval Fichadia, Nikeeta Shah, et al. · Communications in computer and information science
Performance Evaluation of Parallel Processing Adder Against Basic Adders on FPGAs
2024 · Dhaval Fichadia, Kishor Purohit, et al. · Communications in computer and information science
IR Drop Mitigation Methodologies in 90nm Technology Node for Networking Chip
2023 · Dipesh Panchal, Chandni Patel, et al. · IEEE International Symposium on Smart Electronic Systems (iSES)
TAP (Time, Area, and Power) trade off at lower geometries in data center ASIC: A deep dive into executional view and results
2020 · Ruchita Shah*, Nilesh Ranpura*, et al. · CRC Press eBooks
Performance evaluation of 16 nm FinFET based NAND and D flip-flop using BSIM-CMG model
2016 · B Soni, G Aryan, et al. · International Conference Communication and Computing Systems
Works count: 30
Citation count: 38
H-index: 4
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