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Rituraj Singh Rathore
Observed names:
R. Rathore,
Rituraj S. Rathore
Institutions:
Poornima University,
Mody University of Science and Technology
Observed institutions:
National Institute of Technology Hamirpur,
Central Electronics Engineering Research Institute,
Poornima University,
Engineering College, Ajmer,
Council of Scientific and Industrial Research,
Mody University of Science and Technology,
University of KwaZulu-Natal
show all 7
ORCID:
0000-0002-6178-895X
Observed ORCIDs:
0000-0002-6178-895X,
0000-0003-3904-4919
OpenAlex ID:
A5007152241
New low-power techniques: Leakage Feedback with Stack & Sleep Stack with Keeper
2010
·
Pankaj Kr. Pal
, Rituraj S. Rathore
, et al.
·
International Conference on Computer and Communication Technology
·
26
Influence of plastic waste on the performance of mortar and concrete: A review
2021
·
Rituraj Singh Rathore
, Harshwardhan Singh Chouhan
, et al.
·
Materials Today Proceedings
·
20
Investigation of metal-gate work-function variability in FinFET structures and implications for SRAM cell design
2017
·
Rituraj Singh Rathore
, Ashwani K. Rana
·
Superlattices and Microstructures
·
19
Impact of line edge roughness on the performance of 14-nm FinFET: Device-circuit Co-design
2017
·
Rituraj Singh Rathore
, Ashwani K. Rana
·
Superlattices and Microstructures
·
17
Impact of High-k Spacer on Device Performance of Nanoscale Underlap Fully Depleted SOI MOSFET
2017
·
Rajneesh Sharma
, Rituraj S. Rathore
, et al.
·
Journal of Circuits Systems and Computers
·
14
Line edge roughness induced threshold voltage variability in nano-scale FinFETs
2017
·
Rituraj Singh Rathore
, Rajneesh Sharma
, et al.
·
Superlattices and Microstructures
·
14
Threshold voltage variability induced by statistical parameters fluctuations in nanoscale bulk and SOI FinFETs
2017
·
Rituraj Singh Rathore
, Ashwani K. Rana
, et al.
·
International Conference on Signal Processing, Computing and Control (ISPCC)
·
9
Impact of Work Function Fluctuations on Threshold Voltage Variability in a Nanoscale FinFETs
2016
·
Rituraj Singh Rathore
, Rajneesh Sharma
, et al.
·
IEEE International Symposium on Nanoelectronic and Information Systems (iNIS)
·
7
Simulation, fabrication and characterization of Dual-Gate MOSFET test structures
2015
·
S. Sinha
, R. Rathore
, et al.
·
International Symposium on Physics and Technology of Sensors
·
5
Effect of Metal Gate Work Function Variation on Underlap FinFET
2022
·
Rituraj S. Rathore
, Viranjay M. Srivastava
·
International Spring Seminar on Electronics Technology
·
4
Mechanical and Microstructural Analysis of Cement Mortar Mixes Using PET Plastic Waste
2024
·
Rituraj Singh Rathore
, Divya Prakash
, et al.
·
IOP Conference Series Earth and Environmental Science
·
3
Device- and circuit-level variability due to random discrete dopant in resist- and spacer-defined nanoscale FinFETs
2018
·
Rituraj Singh Rathore
, Ashwani K. Rana
·
Journal of Micro/Nanopatterning Materials and Metrology
·
3
Nanoscale Static Random-Access-Memory Design Using Strained Underlap Ultra Thin Silicon on Insulator MOSFET for Improved Performance
2017
·
Rajneesh Sharma
, Rituraj Singh Rathore
, et al.
·
Journal of Nanoelectronics and Optoelectronics
·
3
Impact of Oxide Thickness Fluctuation for Resist- and Spacer-Defined FinFETs
2022
·
Rituraj S. Rathore
, Ashwani K. Rana
, et al.
·
IEEE Latin American Electron Devices Conference (LAEDC)
·
2
Regression Analysis of Static Noise Margin and Transconductance for Underlap Lengths of FinFET
2022
·
Rituraj S. Rathore
, Viranjay M. Srivastava
·
International Spring Seminar on Electronics Technology
·
2
(Digital Presentation) Influence of Fin Width Modulation on Nanoscale FinFET
2022
·
Rituraj S. Rathore
, Viranjay M. Srivastava
·
ECS Transactions
·
1
Threshold voltage variability induced by spacer- and resist-defined patterning techniques in nanoscale FinFETs
2017
·
Rituraj Singh Rathore
, Rajneesh Sharma
, et al.
·
Journal of Micro/Nanopatterning Materials and Metrology
·
1
Performance Analysis of CNTs as an Application for Future VLSI Interconnects
2012
·
Sandeep Sharma
, Rajeevan Chandel
, et al.
·
Microelectronics and solid state electronics
·
1
Analysis of Source-and-Drain Doping for the Underlapped FinFET
2024
·
Rituraj S. Rathore
, Viranjay M. Srivastava
·
IEEE International Conference on Omni-layer Intelligent Systems (COINS)
A design study of embedded system for a hardware assembly of snake and ladder game
2023
·
Journal Editor, Pratibodh -
, Vikas Sharma
, et al.
·
PRATIBODH
PDF
Effect of Multi-fin with Independent LER on Intrinsic Statistical Variability Sources
2023
·
Rituraj S. Rathore
, Viranjay M. Srivastava
·
International Journal of Electrical and Electronic Engineering & Telecommunications
PDF
(Digital Presentation) Influence of Fin Width Modulation on Nanoscale FinFET
2022
·
Rituraj S. Rathore
, Viranjay M. Srivastava
·
ECS Meeting Abstracts
A Low-Power Sample-and-Hold Amplifier using 0.05- µm CMOS Technology
2013
·
Rituraj Singh Rathore
, Vinod Kumar
, et al.
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Works count:
23
Citation count:
151
H-index:
7
I10-index:
6
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