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Chokkakula Ganesh

Observed names: CH. Ganesh, Ch Ganesh, Ch. Ganesh, Chokkakula. Ganesh, Ganesh Chokkakula
ORCID: 0000-0001-9805-3968
Observed ORCID: 0000-0001-9805-3968
OpenAlex ID: A5007589436
Design of low power and high speed modified carry select adder for 16 bit Vedic Multiplier
2014 · Y Bhavani Prasad, Ganesh Chokkakula, et al. · International Conference on Information Communication and Embedded Systems · 19
A Novel Design of Area Efficient Full Adder Architecture Using Reversible Logic Gates
2024 · Chokkakula Ganesh, Aruru Sai Kumar, et al. · International Conference on Devices, Circuits and Systems (ICDCS) · 15
Reconfigurable negative bit line collapsed supply write-assist for 9T-ST static random access memory cell
2023 · Chokkakula Ganesh, Fazal Noorbasha, et al. · International Journal of Power Electronics and Drive Systems/International Journal of Electrical and Computer Engineering · 9
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Implementation of N-Point FFT/IFFT processor based on Radix-2 Using FPGA
2022 · Kota Murali Mohan, K. Naresh, et al. · International Conference on Recent Trends in Microelectronics, Automation, Computing and Communications Systems (ICMACC) · 9
Thermal Stability Analysis of Single-Ended 9T-ST Robust SRAM Cell for Near-Threshold Operation
2021 · Chokkakula Ganesh, K. S. N. Murthy · International Journal of Nanoscience · 8
A Novel Design of High Performance Two-Stage Operational Amplifier using CMOS Technology
2024 · Chokkakula Ganesh, Aruru Sai Kumar, et al. · International Conference on Integrated Circuits and Communication Systems (ICICACS) · 6
Performance and Stability Analysis of Built-In Self-Read and Write Assist 10T SRAM Cell
2023 · Chokkakula Ganesh, Fazal Noorbasha · Active and Passive Electronic Components · 6
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0.91 V reference, 3.3 ppm/°C Sub-BGR with second-order compensation and improved PSRR
2025 · Chokkakula Ganesh, Satheesh Kumar S, et al. · Scientific Reports · 4
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A novel design of high-speed write assist design for single-stacked 9T-ST SRAM
2025 · Chokkakula Ganesh, A. Sai Kumar, et al. · Microsystem Technologies · 4
Principle Study of MoS2 FET at lower Channel Lengths
2024 · Aruru Sai Kumar, V. Bharath Srinivasulu, et al. · Journal of Physics Conference Series · 4
Design and simulation of tunable bandstop filters by integrating RF MEMS shunt switch for K-band applications
2024 · Sk Shoukath Vali, G. Shanthi, et al. · Microsystem Technologies · 4
ASIC implementation of high speed pipelined DDR SDRAM controller
2014 · N Satish Reddy, Ganesh Chokkakula, et al. · International Conference on Information Communication and Embedded Systems · 4
Design of Logic Level Pruning Approximate Arithmetic Circuits Using TIGFET
2025 · Kattekola Naresh, Y. Padma Sai, et al. · Circuits Systems and Signal Processing · 3
Hybrid current mirror-voltage latch sense amplifier with offset correction for enhanced yield in process-sensitive SRAM
2025 · Chokkakula Ganesh, A. Murali, et al. · Results in Engineering · 3
Design and analysis of 8T SRAM with assist schemes (UDVS) in 45nm CMOS
2017 · Ganesh Chokkakula, N. Satish Reddy, et al. · International Conference on Circuit, Power and Computing Technologies · 3
RTL-to-GDSII Implementation of a Register Processor Top-Level Design in 28nm Technology
2025 · Govindu Vikas, Ch. Ganesh, et al. · International Conference on Emerging Applications of Material Science and Technology (ICEAMST) · 2
A precision 0.72 V sub-bandgap reference with 5.02 ppm/°C TC and optimized line and PSR characteristics
2026 · Chokkakula Ganesh, V Krishnasree, et al. · Results in Engineering · 1
Comparison and Analysis of Dynamic Comparator Using LECTOR and GALEOR Techniques with 180nm and 45nm Technologies
2025 · K L V Ramana Kumari, Ch. Ganesh, et al. · Devices for Integrated Circuit (DevIC) · 1
High-Performance ASIC Design for Pipelined DDR2 SDRAM Controllers
2025 · Chokkakula Ganesh, SK. Shoukath Vali, et al. · Devices for Integrated Circuit (DevIC) · 1
Design And Implementation of Hybrid Memory Logic Built-In Self-Test Architecture
2025 · Chokkakula Ganesh, A. Murali, et al. · Advances in computer science research · 1
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Design and implementation of a high-performance Current Starved Voltage Controlled Oscillator (VCO) for PLL
2024 · Chokkakula Ganesh, Mangalapally Naveen Kumar, et al. · AIP conference proceedings · 1
Reconfigurable Negative Bit Line Collapsed Supply Write Assist for 9T-ST SRAM Cell
2022 · Chokkakula Ganesh, K. S.N. Murthy · Research Square · 1
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Optimized reversible QCA full adder subtractor for low latency and energy efficiency
2026 · Aruru Sai Kumar, Chokkakula Ganesh, et al. · Scientific Reports
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A low-power CMOS VCO with 3–13.7 GHz tuning and –89.6 dB/Hz phase noise using current-starved negative skew topology
2026 · Chokkakula Ganesh, Asisa Kumar Panigrahy, et al. · Analog Integrated Circuits and Signal Processing
Implementations of a novel approximate architecture for 2D convolution for image processing applications
2026 · Kattekola Naresh, Ch Ganesh, et al. · Physica Scripta
Works count: 36
Citation count: 109
H-index: 6
I10-index: 2
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