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K. Sridharan

Observed names: K Sridharan, K. SRIDHARAN, Krishnamurthy Sridharan, Sridharan K., Sridharan, K, Sridharan, Krishnamurthy
ORCID: 0000-0001-5279-7830
Observed ORCID: 0000-0001-5279-7830
OpenAlex ID: A5008124905
50 Years of CORDIC: Algorithms, Architectures, and Applications
2009 · P.K. Meher, J. Valls, et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 582
Low Complexity Design of Ripple Carry and Brent–Kung Adders in QCA
2011 · Vikramkumar Pudi, K. Sridharan · IEEE Transactions on Nanotechnology · 229
A Synthesis Methodology for Ternary Logic Circuits in Emerging Device Technologies
2017 · B. Srinivasu, K. Sridharan · IEEE Transactions on Circuits and Systems I Regular Papers · 100
Efficient Design of a Hybrid Adder in Quantum-Dot Cellular Automata
2010 · Vikramkumar Pudi, K. Sridharan · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 92
Efficient CORDIC Algorithms and Architectures for Low Area and High Throughput Implementation
2009 · Leena Vachhani, K. Sridharan, et al. · IEEE Transactions on Circuits & Systems II Express Briefs · 73
Low-Complexity Multiternary Digit Multiplier Design in CNTFET Technology
2016 · B. Srinivasu, K. Sridharan · IEEE Transactions on Circuits & Systems II Express Briefs · 61
New Decomposition Theorems on Majority Logic for Low-Delay Adder Designs in Quantum Dot Cellular Automata
2012 · Vikramkumar Pudi, K. Sridharan · IEEE Transactions on Circuits & Systems II Express Briefs · 54
Design of Arithmetic Circuits in Quantum Dot Cellular Automata Nanotechnology
2015 · K. Sridharan, Vikramkumar Pudi · Studies in computational intelligence · 53
Efficient Multiternary Digit Adder Design in CNTFET Technology
2013 · K. Sridharan, Sundaraiah Gurindagunta, et al. · IEEE Transactions on Nanotechnology · 53
Low-Power and High-Performance Ternary SRAM Designs With Application to CNTFET Technology
2021 · B. Srinivasu, K. Sridharan · IEEE Transactions on Nanotechnology · 52
Efficient FPGA Realization of CORDIC With Application to Robotic Exploration
2009 · L. Vachhani, K. Sridharan, et al. · IEEE Transactions on Industrial Electronics · 42
Majority Logic Formulations for Parallel Adder Designs at Reduced Delay and Circuit Complexity
2017 · Vikramkumar Pudi, K. Sridharan, et al. · IEEE Transactions on Computers · 41
Mobile Robot Navigation Through a Hardware-Efficient Implementation for Control-Law-Based Construction of Generalized Voronoi Diagram
2010 · L. Vachhani, Arun D. Mahindrakar, et al. · IEEE/ASME Transactions on Mechatronics · 38
Carbon nanotube FET‐based low‐delay and low‐power multi‐digit adder designs
2016 · B. Srinivasu, K. Sridharan · IET Circuits Devices & Systems · 37
A Bit-Serial Pipelined Architecture for High-Performance DHT Computation in Quantum-Dot Cellular Automata
2014 · Vikramkumar Pudi, K. Sridharan · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 37
A Resource-Efficient Multiplierless Systolic Array Architecture for Convolutions in Deep Networks
2019 · Yashrajsinh Parmar, K. Sridharan · IEEE Transactions on Circuits & Systems II Express Briefs · 36
Real-Time SURF-Based Video Stabilization System for an FPGA-Driven Mobile Robot
2016 · Tahiyah Shene, Krishnamurthy Sridharan, et al. · IEEE Transactions on Industrial Electronics · 36
The design and development of a web-based data acquisition system
2002 · B. Rajesh Kumar, K. Sridharan, et al. · IEEE Transactions on Instrumentation and Measurement · 28
The Design of a Hardware Accelerator for Real-Time Complete Visibility Graph Construction and Efficient FPGA Implementation
2005 · K. Sridharan, T.K. Priya · IEEE Transactions on Industrial Electronics · 27
A Transistor-Level Probabilistic Approach for Reliability Analysis of Arithmetic Circuits With Applications to Emerging Technologies
2017 · Bodapati Srinivasu, K. Sridharan · IEEE Transactions on Reliability · 25
CORDIC-Based Azimuth Calculation and Obstacle Tracing via Optimal Sensor Placement on a Mobile Robot
2015 · Pranjal Vyas, Leena Vachhani, et al. · IEEE/ASME Transactions on Mechatronics · 23
Hardware-Efficient Prediction-Correction-Based Generalized-Voronoi-Diagram Construction and FPGA Implementation
2008 · L. Vachhani, K. Sridharan · IEEE Transactions on Industrial Electronics · 21
Efficient design of Baugh-Wooley multiplier in Quantum-Dot Cellular Automata
2013 · Vikramkumar Pudi, K. Sridharan · IEEE International Conference on Nanotechnology (IEEE-NANO) · 19
Measures of intensity of collision between convex objects and their efficient computation
1991 · S.S. Keerthi, K. Sridharan · NOT FOUND REPOSITORY (Indian Institute of Science Bangalore) · 18
A hardware-efficient scheme and FPGA realization for computation of single pair shortest path for a mobile automaton
2006 · T.K. Priya, P. Rajesh Kumar, et al. · Microprocessors and Microsystems · 17
Works count: 126
Citation count: 2,211
H-index: 21
I10-index: 40
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