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Author

Michael Pellauer

Observed names: M. Pellauer, Pellauer, Michael, Pellauer, Michael (Michael Ignatius), Pellauer, Michael Ignatius
Observed institutions: Nvidia (United Kingdom), Georgia Institute of Technology, Intel (United States), Princeton University, Nvidia (United States), MIT Computer Science and Artificial Intelligence Laboratory, Massachusetts Institute of Technology, University of California, Davis
ORCID: 0000-0002-5305-4307
Observed ORCID: 0000-0002-5305-4307
OpenAlex ID: A5009910914
Understanding Reuse, Performance, and Hardware Cost of DNN Dataflow: A Data-Centric Approach
2019 · Hyoukjun Kwon, Prasanth Chatarasi, et al. · IEEE/ACM International Symposium on Microarchitecture (MICRO) · 327
ExTensor: An Accelerator for Sparse Tensor Algebra
2019 · Kartik Hegde, Hadi Asghari-Moghaddam, et al. · IEEE/ACM International Symposium on Microarchitecture (MICRO) · 260
MAESTRO: A Data-Centric Approach to Understand Reuse, Performance, and Hardware Cost of DNN Mappings
2020 · Hyoukjun Kwon, Prasanth Chatarasi, et al. · IEEE Micro · 232
UCNN: Exploiting Computational Reuse in Deep Neural Networks via Weight Repetition
2018 · Kartik Hegde, Jiyong Yu, et al. · Proceedings - International Symposium on Computer Architecture/Proceedings · 196
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Heterogeneous Dataflow Accelerators for Multi-DNN Workloads
2021 · Hyoukjun Kwon, Liangzhen Lai, et al. · IEEE International Symposium on High-Performance Computer Architecture (HPCA) · 159
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Triggered instructions: a control paradigm for spatially-programmed architectures
2013 · Angshuman Parashar, Michael Pellauer, et al. · Proceedings - International Symposium on Computer Architecture/Proceedings · 120
HAsim: FPGA-based high-detail multicore simulation using time-division multiplexing
2011 · Michael Pellauer, Michael Adler, et al. · IEEE International Symposium on High-Performance Computer Architecture (HPCA) · 104
Buffets: An Efficient and Composable Storage Idiom for Explicit Decoupled Data Orchestration
2019 · Michael Pellauer, Yakun Sophia Shao, et al. · International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) · 96
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Leap scratchpads: automatic memory and cache management for reconfigurable logic
2011 · Michael Adler, Kermin E. Fleming, et al. · ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) · 94
PipeCheck: Specifying and Verifying Microarchitectural Enforcement of Memory Consistency Models
2014 · Daniel Lustig, Michael Pellauer, et al. · IEEE/ACM International Symposium on Microarchitecture (MICRO) · 80
Flexagon: A Multi-dataflow Sparse-Sparse Matrix Multiplication Accelerator for Efficient DNN Processing
2023 · Francisco Muñoz-Martínez, Raveesh Garg, et al. · International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) · 76
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CCICheck: using µhb graphs to verify the coherence-consistency interface
2015 · Yatin A. Manerkar, Daniel Lustig, et al. · IEEE/ACM International Symposium on Microarchitecture (MICRO) · 52
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ArMOR: defending against memory consistency model mismatches in heterogeneous architectures
2015 · Daniel Lustig, Caroline Trippel, et al. · Proceedings - International Symposium on Computer Architecture/Proceedings · 52
Hardware Acceleration of Matrix Multiplication on a Xilinx FPGA
2007 · Nirav Dave, Kermin Fleming, et al. · ACM/IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE) · 50
TriCheck: Memory Model Verification at the Trisection of Software, Hardware, and ISA
2017 · Caroline Trippel, Yatin A. Manerkar, et al. · International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) · 48
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Triggered instructions: a control paradigm for spatially-programmed architectures
2013 · Angshuman Parashar, Michael Pellauer, et al. · ACM SIGARCH Computer Architecture News · 46
Heracles: a tool for fast RTL-based design space exploration of multicore processors
2013 · Michel A. Kinsy, Michael Pellauer, et al. · ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) · 44
A modular digital VLSI flow for high-productivity SoC design
2018 · Brucek Khailany, Evgeni Khmer, et al. · ACM/IEEE Design Automation Conference (DAC) · 42
Quick Performance Models Quickly: Closely-Coupled Partitioned Simulation on FPGAs
2008 · Michael Pellauer, Muralidaran Vijayaraghavan, et al. · IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) · 40
Synthesis of synchronous assertions with guarded atomic actions
2005 · M. Pellauer, M. Liz, et al. · ACM/IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE) · 39
Leveraging latency-insensitivity to ease multiple FPGA design
2012 · Kermin Elliott Fleming, Michael Adler, et al. · ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) · 36
Marvel: A Data-Centric Approach for Mapping Deep Learning Operators on Spatial Accelerators
2021 · Prasanth Chatarasi, Hyoukjun Kwon, et al. · ACM Transactions on Architecture and Code Optimization · 35
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Heracles: Fully Synthesizable Parameterized MIPS-Based Multicore System
2011 · Michel A. Kinsy, Michael Pellauer, et al. · International Conference on Field Programmable Logic and Applications (FPL) · 35
Understanding Reuse, Performance, and Hardware Cost of DNN Dataflows: A Data-Centric Approach Using MAESTRO
2018 · Kwon, Hyoukjun, Chatarasi, Prasanth, et al. · arXiv (Cornell University) · 34
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A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs
2008 · Michael Pellauer, Muralidaran Vijayaraghavan, et al. · ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) · 34
Works count: 104
Citation count: 2,932
H-index: 30
I10-index: 48
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