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W.D. Dettloff

Observed names: W. Dettloff, Wayne D Dettloff, Wayne D. Detloff, Wayne Dettloff
OpenAlex ID: A5010306462
A VLSI fuzzy logic controller with reconfigurable, cascadable architecture
1990 · H. Watanabe, W.D. Dettloff, et al. · IEEE Journal of Solid-State Circuits · 262
A 32mW 7.4Gb/s protocol-agile source-series-terminated transmitter in 45nm CMOS SOI
2010 · Wayne D Dettloff, John C Eble, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 47
VLSI fuzzy chip and inference accelerator board systems
2002 · H. Watanabe, J.R. Symon, et al. · IEEE International Symposium on Multiple-Valued Logic (ISMVL) · 44
A 6.4-Gb/s Near-Ground Single-Ended Transceiver for Dual-Rank DIMM Memory Interface Systems
2013 · Michael Bucher, Ravi T. Kollipara, et al. · IEEE Journal of Solid-State Circuits · 35
A VLSI fuzzy logic inference engine for real-time process control
1989 · W.D. Dettloff, K.E. Yount · Custom Integrated Circuits Conference · 33
BioSCAN: a VLSI-based system for biosequence analysis
2002 · C.T. White, R.K. Singh, et al. · IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD) · 32
A 5.6Gb/s 2.4mW/Gb/s bidirectional link with 8ns power-on
2011 · Jared Zerbe, Barry Daly, et al. · Symposium on VLSI Circuits · 21
A 5 Gb/s Link With Matched Source Synchronous and Common-Mode Clocking Techniques
2011 · Jared Zerbe, Barry Daly, et al. · IEEE Journal of Solid-State Circuits · 18
A 6.4Gb/s near-ground single-ended transceiver for dual-rank DIMM memory interface systems
2013 · K. Kaviani, M. Bucher, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 13
VLSI fuzzy chip and inference accelerator board systems
1992 · Hiroyuki Watanabe, Wayne D. Detloff, et al. · John Wiley & Sons, Inc. eBooks · 12
Fuzzy Logic Inference Processor for Real Time Control: A Second Generation Full Custom Design,
1986 · Hiroyuki Watanabe, W.D. Dettloff · NASA STI/Recon Technical Report N · 12
A fuzzy logic controller with reconfigurable, cascadable architecture
2003 · W.D. Dettloff, K.E. Yount, et al. · IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD) · 9
The Omnitest system: a no-generate, no-compile, interactive test methodology
2003 · W.D. Dettloff, M.D. Tebbs · IEEE International Test Conference (ITC) · 8
A 50MHz 1.5M Transistor ASIC For Biosequence Analysis
1991 · W.D. Dettloff, R.K. Singh, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 5
A 6.4/3.2/1.6 Gb/s low power interface with all digital clock multiplier for on-the-fly rate switching
2012 · Masum Hossain, Kambiz Kaviani, et al. · Custom Integrated Circuits Conference · 4
A 5Gb/s link with clock edge matching and embedded common mode clock for low power interfaces
2010 · Jared Zerbe, Barry Daly, et al. · Symposium on VLSI Circuits · 1
A parallel processor ASIC for real time pattern recognition
2002 · M.T. Mostafavi, S. Vishin, et al. · Euro ASIC Conference (EURO ASIC) · 1
Works count: 17
Citation count: 557
H-index: 11
I10-index: 11
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