Get started
Author

Soumya Eachempati

Observed name: S. Eachempati
OpenAlex ID: A5011811213
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs
2009 · Reetuparna Das, Soumya Eachempati, et al. · IEEE International Symposium on High-Performance Computer Architecture (HPCA) · 195
MIRA
2008 · Dongkook Park, Soumya Eachempati, et al. · ACM SIGARCH Computer Architecture News · 179
A case for dynamic frequency tuning in on-chip networks
2009 · Asit K. Mishra, Reetuparna Das, et al. · IEEE/ACM International Symposium on Microarchitecture (MICRO) · 119
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
2008 · Dongkook Park, Soumya Eachempati, et al. · Proceedings - International Symposium on Computer Architecture/Proceedings · 111
Assessing carbon nanotube bundle interconnect for future FPGA architectures
2007 · Soumya Eachempati, Arthur Nieuwoudt, et al. · Design, Automation, and Test in Europe · 57
Expression of Concern: Assessing Carbon Nanotube Bundle Interconnect for Future FPGA Architectures
2007 · Soumya Eachempati, Arthur Nieuwoudt, et al. · Design, Automation, and Test in Europe · 55
Reconfigurable BDD based quantum circuits
2008 · Soumya Eachempati, Vinay Saripalli, et al. · IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) · 29
Automated mapping for reconfigurable single-electron transistor arrays
2011 · Yung-Chih Chen, Soumya Eachempati, et al. · ACM/IEEE Design Automation Conference (DAC) · 26
RAFT: A router architecture with frequency tuning for on-chip networks
2010 · Asit K. Mishra, Aditya Yanamandra, et al. · Journal of Parallel and Distributed Computing · 25
A Synthesis Algorithm for Reconfigurable Single-Electron Transistor Arrays
2013 · Yung-Chih Chen, Soumya Eachempati, et al. · ACM Journal on Emerging Technologies in Computing Systems · 18
Predicting the performance and reliability of future field programmable gate arrays routing architectures with carbon nanotube bundle interconnect
2009 · S. Eachempati, N. Vijaykrishnan, et al. · IET Circuits Devices & Systems · 16
Optimizing power and performance for reliable on-chip networks
2010 · Aditya Yanamandra, Soumya Eachempati, et al. · Asia and South Pacific Design Automation Conference (ASP-DAC) · 15
Leveraging Emerging Technology Through Architectural Exploration for the Routing Fabric of Future FPGAs
2010 · Soumya Eachempati, Aman Gayasen, et al. · Springer eBooks · 5
Reliability Aware Performance and Power Optimization in DVFS-Based On-Chip Networks
2010 · Aditya Yanamandra, Soumya Eachempati, et al. · IGI Global eBooks · 3
Impact of Process Variations on Carbon Nanotube Bundle Interconnect for Future FPGA Architectures
2007 · S. Eachempati, N. Vijaykrishnan, et al. · IEEE Computer Society Annual Symposium on VLSI · 3
Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution network
2009 · Yuan Xie, Soumya Eachempati, et al. · IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) · 1
HeTERO: Hybrid Topology Exploration for RF-Based On- Chip Networks
2018 · Soumya Eachempati, Reetuparna Das, et al. · CRC Press eBooks
Three-dimensional On-chip Interconnect Architectures
2010 · Soumya Eachempati, Dongkook Park, et al. · Chapman & Hall/CRC computational science series/Chapman & Hall/CRC computational science
Non-silicon logic elements on silicon for extreme voltage scaling
2010 · S. Datta, A. Ali, et al. · Silicon Nanoelectronics Workshop (SNW)
Influence of emerging technologies on interconnect architectures
2010 · Vijaykrishnan Naraynan, Soumya Eachempati
Works count: 20
Citation count: 857
H-index: 12
I10-index: 12
Year
Topic
Type