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Mark Cairnie
Observed names:
Cairnie, Mark,
Cairnie, Mark A. Jr.
Institution:
Virginia Tech
Observed institution:
Virginia Tech
ORCID:
0000-0002-9301-7981
Observed ORCID:
0000-0002-9301-7981
OpenAlex ID:
A5011999584
10 kV SiC MOSFET Power Module with Double-Sided Jet-Impingement Cooling
2023
·
Mark Cairnie
, Christina DiMarino
·
IEEE Applied Power Electronics Conference and Exposition (APEC)
·
17
Bayesian Optimization of PCB-Integrated Field Grading for a High-Density 10 kV SiC Power Module Interface
2021
·
Mark Cairnie
, Christina DiMarino
·
IEEE Transactions on Power Electronics
·
15
Optimization of Electric-Field Grading Plates in a PCB-Integrated Bus Bar for a High-Density 10 kV SiC MOSFET Power Module
2021
·
Mark Cairnie
, Christina DiMarino
·
IEEE Applied Power Electronics Conference and Exposition (APEC)
·
7
Monte Carlo Statistical Tolerance Analysis of a Parallel-Plate Multichip Power Module
2024
·
Danielle Lester
, Mark Cairnie
, et al.
·
IEEE Transactions on Power Electronics
·
6
Thermal and Thermomechanical Analysis of a 10 kV SiC MOSFET Package with Double-Sided Cooling
2021
·
Mark Cairnie
, Jacob Gersh
, et al.
·
IEEE Workshop on Wide Bandgap Power Devices and Applications
·
6
PCIM Europe Conference Proceedings
2024
·
Cairnie, Mark A. Jr.
, Kamalapur, Aakash
, et al.
·
VTechWorks (Virginia Tech)
·
4
PDF
Reduce-Order Analysis and Circuit-Level Cost Function for the Numerical Optimization of Power Electronics Modules
2021
·
Mark Cairnie
, Christina DiMarino
, et al.
·
IEEE Workshop on Control and Modelling of Power Electronics (COMPEL)
·
2
Gate Driver for 10 kV SiC MOSFET Power Module with High-Speed Current Sensing
2021
·
Mark Cairnie
, Christina DiMarino
·
IEEE Energy Conversion Congress and Exposition (ECCE)
·
2
Coaxial Gate/Kelvin Interconnects for Reduced Gate Loop Inductance and Common Source Mutual Inductance in Power Semiconductor Packages
2026
·
Jack Knoll
, Mark Cairnie
, et al.
·
IEEE Transactions on Components Packaging and Manufacturing Technology
·
1
PDF
Dimensional Parasitics Absorption in Capacitively-Isolated Ćuk Converter for Medium-Voltage High Step-Down Converters
2025
·
Aakash Kamalapur
, Jung-Soo Bae
, et al.
·
IEEE Applied Power Electronics Conference and Exposition (APEC)
·
1
Bayesian Optimization of PCB-Embedded Electric-Field Grading Geometries for a 10 kV SiC MOSFET Power Module
2021
·
Mark Cairnie
·
VTechWorks (Virginia Tech)
·
1
Scaled: Substation in a cable for adaptable low-cost electrical distribution
2025
·
Mark Cairnie
, Christina DiMarino
·
Open Access Government
PDF
Thermal Modeling and Limitations for Power Electronics Embedded in Medium-Voltage Cables
2025
·
Mark Cairnie
, Christina DiMarino
, et al.
·
IEEE Transactions on Power Electronics
Coaxially Nested 3.3 kV SiC MOSFET Packages with Uniform Interpackage Electric Field Distribution
2025
·
Jack Knoll
, Mark Cairnie
, et al.
·
IEEE Applied Power Electronics Conference and Exposition (APEC)
Beyond Two-Dimensional Losses in Solenoidal Inductors with Distributed Gaps
2024
·
Rajaie Nassar
, Qingrui Yuchi
, et al.
·
IEEE Energy Conversion Congress and Exposition (ECCE)
Medium-Voltage Co-Packaged Charge-Balanced GaN SHJ-SBD with a SiC MOSFET in a Chopper Power Module
2023
·
Danielle Lester
, Mark Cairnie
, et al.
·
IEEE Energy Conversion Congress and Exposition (ECCE)
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Works count:
17
Citation count:
62
H-index:
5
I10-index:
2
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