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Je-Min Hung

Observed name: Je-Ming Hung
ORCID: 0000-0002-2721-1401
Observed ORCID: 0000-0002-2721-1401
OpenAlex ID: A5013384597
Challenges and Trends of SRAM-Based Computing-In-Memory for AI Edge Devices
2021 · Chuan-Jia Jhang, Cheng-Xin Xue, et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 312
16.1 A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91 to 195.7TOPS/W for Tiny AI Edge Devices
2021 · Cheng-Xin Xue, Je-Min Hung, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 188
A CMOS-integrated compute-in-memory macro based on resistive random-access memory for AI edge devices
2020 · Cheng-Xin Xue, Yen-Cheng Chiu, et al. · Nature Electronics · 182
Fusion of memristor and digital compute-in-memory processing for energy-efficient edge computing
2024 · Tai-Hao Wen, Je-Min Hung, et al. · Science · 140
An 8-Mb DC-Current-Free Binary-to-8b Precision ReRAM Nonvolatile Computing-in-Memory Macro using Time-Space-Readout with 1286.4-21.6TOPS/W for Edge-AI Devices
2022 · Je-Min Hung, Yen-Hsiang Huang, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 137
A four-megabit compute-in-memory macro with eight-bit precision based on CMOS and resistive random-access memory for AI edge devices
2021 · Je-Min Hung, Cheng-Xin Xue, et al. · Nature Electronics · 124
A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors
2020 · Yen-Cheng Chiu, Zhixiao Zhang, et al. · IEEE Journal of Solid-State Circuits · 93
A Nonvolatile Al-Edge Processor with 4MB SLC-MLC Hybrid-Mode ReRAM Compute-in-Memory Macro and 51.4-251TOPS/W
2023 · Wei-Hsing Huang, Tai-Hao Wen, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 82
8-b Precision 8-Mb ReRAM Compute-in-Memory Macro Using Direct-Current-Free Time-Domain Readout Scheme for AI Edge Devices
2022 · Je-Min Hung, Tai-Hao Wen, et al. · IEEE Journal of Solid-State Circuits · 81
Challenges and Trends of Nonvolatile In-Memory-Computation Circuits for AI Edge Devices
2021 · Je-Min Hung, Chuan-Jia Jhang, et al. · IEEE Open Journal of the Solid-State Circuits Society · 57
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Challenges and Trends inDeveloping Nonvolatile Memory-Enabled Computing Chips for Intelligent Edge Devices
2020 · Je-Min Hung, Xueqing Li, et al. · IEEE Transactions on Electron Devices · 51
13.4 A 22nm 1Mb 1024b-Read and Near-Memory-Computing Dual-Mode STT-MRAM Macro with 42.6GB/s Read Bandwidth for Security-Aware Mobile Devices
2020 · Tung-Cheng Chang, Yen-Cheng Chiu, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 46
A 28nm Nonvolatile AI Edge Processor using 4Mb Analog-Based Near-Memory-Compute ReRAM with 27.2 TOPS/W for Tiny AI Edge Devices
2023 · Tai-Hao Wen, Je-Min Hung, et al. · IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 24
A 22-nm 1-Mb 1024-b Read Data-Protected STT-MRAM Macro With Near-Memory Shift-and-Rotate Functionality and 42.6-GB/s Read Bandwidth for Security-Aware Mobile Device
2021 · Yen-Cheng Chiu, Tung-Cheng Chang, et al. · IEEE Journal of Solid-State Circuits · 20
Monolithic 3D+-IC Based Massively Parallel Compute-in-Memory Macro for Accelerating Database and Machine Learning Primitives
2020 · Akshay Krishna Ramanathan, Srivatsa Srinivasa Rangachar, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 12
First Demonstration of Ultrafast Laser Annealed Monolithic 3D Gate-All-Around CMOS Logic and FeFET Memory with Near-Memory-Computing Macro
2020 · Fu-Kuo Hsueh, Je-Min Hung, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 11
CiM3D: Comparator-in-Memory Designs Using Monolithic 3-D Technology for Accelerating Data-Intensive Applications
2021 · Akshay Krishna Ramanathan, Srivatsa Srinivasa Rangachar, et al. · IEEE Journal on Exploratory Solid-State Computational Devices and Circuits · 9
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A 3 nm FinFET 125 TOPS/W-29 TFLOPS/W, 90 TOPS/mm 2 -17 TFLOPS/mm 2 SRAM-Based INT8, and FP16 Digital-CIM Compiler With Support for Multi-Weight Update/Cycle
2025 · Haruki Mori, Je-Min Hung, et al. · IEEE Journal of Solid-State Circuits · 5
Reliable Computing of ReRAM Based Compute-in-Memory Circuits for AI Edge Devices
2022 · Meng-Fan Chang, Je-Ming Hung, et al. · International Conference on Computer Aided Design · 2
A 2nm 234.4 TOPS/W and 511.9 $\text{TOPS}/\text{mm}^{2}$ Digital Computing-in-Memory Compiler with Multiple MAC Units per Weight and Multiple Data Format Support
2026 · Hidehiro Fujiwara, Brian Crafton, et al. · IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
Enhancing DCIM Efficiency with Multi-Storage-Row Architecture for Edge AI Workloads
2025 · Xiaoyu Sun, Haruki Mori, et al. · IEEE Computer Architecture Letters
Works count: 21
Citation count: 1,576
H-index: 14
I10-index: 16
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