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Donatella Sciuto

Observed names: D Sciuto, D. Sciuto, DONATELLA SCIUTO, Donatella Ssciuto, Prof Donatella Sciuto, SCIUTO, DONATELLA, SCIUTO, Donatella, Sciuto Donatella, Sciuto, Donatella
Observed institutions: University of Padua, University of Colorado Boulder, University of Milan, University of Colorado System, University Carlo Cattaneo, Institute of Electrical and Electronics Engineers, Fondazione Politecnico di Milano, Cefriel, École Polytechnique Fédérale de Lausanne, Polytechnic University of Bari, University of Brescia, University of Tübingen, Texas A&M University, Politecnico di Milano
ORCID: 0000-0001-9030-6940
Observed ORCID: 0000-0001-9030-6940
OpenAlex ID: A5014181688
Factors affecting ERP system adoption
2005 · G. Buonanno, P. Faverio, et al. · Journal of Enterprise Information Management · 450
Asymptotic zero-transition activity encoding for address busses in low-power microprocessor-based systems
2002 · L. Benini, G. De Micheli, et al. · ACM Great Lakes Symposium on VLSI (GLSVLSI) · 292
Ant Colony Heuristic for Mapping and Scheduling Tasks and Communications on Heterogeneous Embedded Systems
2010 · Fabrizio Ferrandi, Pier Luca Lanzi, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 157
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Address Bus Encoding Techniques for System-Level Power Optimization
1997 · Luca Benini, Giovanni De Micheli, et al. · 128
BlueSentinel
2014 · Giorgio Conte, Massimo De Marchi, et al. · ACM International Conference on Systems for Energy-Efficient Buildings, Cities, and Transportation (BuildSys) · 96
Implicit test generation for behavioral VHDL models
2002 · F. Ferrandi, F. Fummi, et al. · IEEE International Test Conference (ITC) · 93
Occupancy Detection via iBeacon on Android Devices for Smart Building Management
2015 · A. Corna, L. Fontanab, et al. · Design, Automation, and Test in Europe · 91
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Address bus encoding techniques for system-level power optimization
2002 · L. Benini, G. De Micheli, et al. · Design, Automation, and Test in Europe · 75
Power estimation of embedded systems: a hardware/software codesign approach
1998 · W. Fornaciari, P. Gubian, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 75
Decision-Theoretic Design Space Exploration of Multiprocessor Platforms
2010 · Giovanni Beltrame, Luca Fossati, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 69
Source-level execution time estimation of C programs
2001 · C. Brandolese, W. Fornaciari, et al. · International Symposium on Hardware/Software Codesign (CODES) · 68
Power optimization of system-level address buses based on software profiling
2000 · W. Fornaciari, M. Polentarutti, et al. · International Symposium on Hardware/Software Codesign (CODES) · 68
ASSURE: RTL Locking Against an Untrusted Foundry
2021 · Christian Pilato, Animesh Basak Chowdhury, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 65
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An instruction-level functionally-based energy estimation model for 32-bits microprocessors
2000 · C. Brandolese, W. Fornaciari, et al. · ACM/IEEE Design Automation Conference (DAC) · 63
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Pushing the Level of Abstraction of Digital System Design: A Survey on How to Program FPGAs
2022 · Emanuele Del Sozzo, Davide Conficconi, et al. · ACM Computing Surveys · 60
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ReSP: A Nonintrusive Transaction-Level Reflective MPSoC Simulation Platform for Design Space Exploration
2009 · G. Beltrame, L. Fossati, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 57
Partitioning and Scheduling of Task Graphs on Partially Dynamically Reconfigurable FPGAs
2009 · R. Cordone, F. Redaelli, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 54
Power estimation for architectural exploration of HW/SW communication on system-level buses
1999 · William Fornaciari, Donatella Sciuto, et al. · International Symposium on Hardware/Software Codesign (CODES) · 52
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Internal and External Bitstream Relocation for Partial Dynamic Reconfiguration
2009 · S. Corbetta, M. Morandi, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 49
A design framework to efficiently explore energy-delay tradeoffs
2001 · William Fornaciari, Donatella Sciuto, et al. · International Symposium on Hardware/Software Codesign (CODES) · 48
A Multi-objective Genetic Algorithm for Design Space Exploration in High-Level Synthesis
2008 · Fabrizio Ferrandi, Pier Luca Lanzi, et al. · IEEE Computer Society Annual Symposium on VLSI · 47
Instruction-level power estimation for embedded VLIW cores
2000 · M. Sami, D. Sciuto, et al. · International Symposium on Hardware/Software Codesign (CODES) · 47
Multi-Accuracy Power and Performance Transaction-Level Modeling
2007 · Giovanni Beltrame, Donatella Sciuto, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 45
A Sensitivity-Based Design Space Exploration Methodology for Embedded Systems
2002 · William Fornaciari, Donatella Sciuto, et al. · Design Automation for Embedded Systems · 45
Design of VHDL-based totally self-checking finite-state machine and data-path descriptions
2000 · C. Bolchini, R. Montandon, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 45
Works count: 676
Citation count: 6,767
H-index: 38
I10-index: 178
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