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Daewon Ha
Observed names:
D. Ha,
D. W. Ha,
D.W. Ha,
Dae-Won Ha,
Damon Ha,
Ha, Daewon
show all 6
Institutions:
Georgia Institute of Technology,
Samsung (South Korea),
Samsung Electronics (South Korea)
Observed institutions:
Georgia Institute of Technology,
Samsung (South Korea),
University of California System,
Samsung Electronics (South Korea),
Hanyang University,
University of California, Berkeley
show all 6
ORCID:
0000-0002-9061-8626
Observed ORCID:
0000-0002-9061-8626
OpenAlex ID:
A5015290434
Progress, Challenges, and Opportunities in Oxide Semiconductor Devices: A Key Building Block for Applications Ranging from Display Backplanes to 3D Integrated Semiconductor Chips
2022
·
Taikyu Kim
, Cheol Hee Choi
, et al.
·
Advanced Materials
·
296
Extremely scaled silicon nano-CMOS devices
2003
·
Leland Chang
, Yang-Kyu Choi
, et al.
·
Proceedings of the IEEE
·
279
Observation of bulk HfO2 defects by spectroscopic ellipsometry
2004
·
Hideki Takeuchi
, Daewon Ha
, et al.
·
Journal of Vacuum Science & Technology A Vacuum Surfaces and Films
·
244
Sub-20 nm CMOS FinFET technologies
2002
·
Yang-Kyu Choi
, N. Lindert
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
197
Revival of Ferroelectric Memories Based on Emerging Fluorite‐Structured Ferroelectrics
2022
·
Ju Yong Park
, Duk‐Hyun Choe
, et al.
·
Advanced Materials
·
196
FinFET process refinements for improved mobility and gate work function engineering
2003
·
Yang-Kyu Choi
, Leland Chang
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
106
Two-bit cell operation in diode-switch phase change memory cells with 90nm technology
2008
·
D.-H. Kang
, J.-H. Lee
, et al.
·
Symposium on VLSI Technology
·
98
Investigation of Gate-Induced Drain Leakage (GIDL) Current in Thin Body Devices: Single-Gate Ultra-Thin Body, Symmetrical Double-Gate, and Asymmetrical Double-Gate MOSFETs
2003
·
Yang-Kyu Choi
, Daewon Ha
, et al.
·
Japanese Journal of Applied Physics
·
94
PDF
Analog reservoir computing via ferroelectric mixed phase boundary transistors
2024
·
Jangsaeng Kim
, Eun Chan Park
, et al.
·
Nature Communications
·
84
PDF
Si FinFET based 10nm technology with multi Vt gate stack for low power and high performance applications
2016
·
H.-J. Cho
, H.S. Oh
, et al.
·
Symposium on VLSI Technology
·
80
Highly manufacturable 7nm FinFET technology featuring EUV lithography for low power and high performance applications
2017
·
Daewon Ha
, C. Yang
, et al.
·
Symposium on VLSI Technology
·
74
Comprehensive Design Guidelines of Gate Stack for QLC and Highly Reliable Ferroelectric VNAND
2023
·
Suhwan Lim
, Taeyoung Kim
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
69
Negative differential capacitance in ultrathin ferroelectric hafnia
2023
·
Sanghyun Jo
, Hyangsook Lee
, et al.
·
Nature Electronics
·
68
Experimental demonstration and modeling of a ferroelectric gate stack with a tunnel dielectric insert for NAND applications
2023
·
Dipjyoti Das
, Hyeonwoo Park
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
63
Molybdenum Gate Technology for Ultrathin-Body MOSFETs and FinFETs
2004
·
D. Ha
, H. Takeuchi
, et al.
·
IEEE Transactions on Electron Devices
·
57
Reliability study of CMOS FinFETs
2004
·
Yang-Kyu Choi
, Daewon Ha
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
57
Nanoscale ultrathin body PMOSFETs with raised selective germanium source/drain
2001
·
Yang-Kyu Choi
, Daewon Ha
, et al.
·
IEEE Electron Device Letters
·
57
Hydrogen annealing effect on DC and low-frequency noise characteristics in CMOS FinFETs
2003
·
Jeong-Soo Lee
, Yang-Kyu Choi
, et al.
·
IEEE Electron Device Letters
·
56
Anomalous junction leakage current induced by STI dislocations and its impact on dynamic random access memory devices
1999
·
Daewon Ha
, Changhyun Cho
, et al.
·
IEEE Transactions on Electron Devices
·
54
True 7nm Platform Technology featuring Smallest FinFET and Smallest SRAM cell by EUV, Special Constructs and 3rd Generation Single Diffusion Break
2018
·
W.C. Jeong
, D.J. Kwon
, et al.
·
Symposium on VLSI Technology
·
51
Tunable work function molybdenum gate technology for FDSOI-CMOS
2003
·
P. Ranade
, Yang-Kyu Choi
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
45
Ferroelectric transistors for low-power NAND flash memory
2025
·
Sijung Yoo
, Taek Jung Kim
, et al.
·
Nature
·
41
Impact of oxygen vacancies on high-κ gate stack engineering
2005
·
H. Takeuchi
, Hiu Yung Wong
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
40
First demonstration of 3-dimensional stacked FET with top/bottom source-drain isolation and stacked n/p metal gate
2023
·
Jaehyun Park
, Wukang Kim
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
38
Gate stack engineering of two-dimensional transistors
2025
·
Yeon Ho Kim
, Donghun Lee
, et al.
·
Nature Electronics
·
36
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Works count:
178
Citation count:
3,627
H-index:
31
I10-index:
73
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