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Author

Jaekwang Yun

Institution: Gachon University
ORCID: 0009-0000-0460-4686
Observed ORCID: 0009-0000-0460-4686
OpenAlex ID: A5016065904
A 78.8fJ/b/mm 12.0Gb/s/Wire Capacitively Driven On-Chip Link Over 5.6mm with an FFE-Combined Ground-Forcing Biasing Technique for DRAM Global Bus Line in 65nm CMOS
2022 · Sangyoon Lee, Jaekwang Yun, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 13
A Low-Power and Low-Noise 20:1 Serializer with Two Calibration Loops in 55-nm CMOS
2019 · Yong-Un Jeong, Joo-Hyung Chae, et al. · IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) · 12
A Low-Power DRAM Transmitter With Phase and Current-Mode Amplitude Equalization to Improve Impedance Matching
2022 · Sangyoon Lee, Yong-Un Jeong, et al. · IEEE Transactions on Circuits & Systems II Express Briefs · 10
A 10 Gb/s/pin Single-Ended Transmitter With Reflection-Aided Duobinary Modulation for Dual-Rank Mobile Memory Interfaces
2021 · Yong-Un Jeong, Sungphil Choi, et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 10
A 370-fJ/b, 0.0056 mm2/DQ, 4.8-Gb/s DQ Receiver for HBM3 with a Baud-Rate Self-Tracking Loop
2019 · Han-Gon Ko, Soyeong Shin, et al. · Symposium on VLSI Circuits · 10
A 9Gb/s Wide Output Range Transmitter With 2D Binary-Segmented Driver and Dual-Loop Calibration for Intra-Panel Interfaces
2020 · Yong-Un Jeong, Jihwan Park, et al. · IEEE Transactions on Circuits & Systems II Express Briefs · 9
A 0.45 pJ/b, 6.4 Gb/s Forwarded-Clock Receiver With DLL-Based Self-Tracking Loop for Unmatched Memory Interfaces
2019 · Soyeong Shin, Han-Gon Ko, et al. · IEEE Transactions on Circuits & Systems II Express Briefs · 7
A 50–1600 MHz Wide–Range Digital Duty–Cycle Corrector With Counter–Based Half–Cycle Delay Line
2023 · Jaewook Kim, Jaekwang Yun, et al. · IEEE Access · 6
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A Single-Ended Impedance-Matched Transmitter With Single Ring-Oscillator-Based Time-Domain ZQ Calibration for Memory Interfaces
2024 · Jaekwang Yun, Sangyoon Lee, et al. · IEEE Journal of Solid-State Circuits · 5
A 0.4-1.7GHz Wide Range Fractional-N PLL Using a Transition-Detection DAC for Jitter Reduction
2020 · Jaekwang Yun, Sangyoon Lee, et al. · IEEE Asian Solid-State Circuits Conference (A-SSCC) · 5
A 0.83-pJ/Bit 6.4-Gb/s HBM Base Die Receiver Using a 45° Strobe Phase for Energy-Efficient Skew Compensation
2019 · Sangyoon Lee, Han-Gon Ko, et al. · IEEE Transactions on Circuits & Systems II Express Briefs · 4
An Energy and Area-Efficient PAM-4 Data Coding Scheme with Embedded Supply Noise Stabilization for Single-Ended Memory Interface
2025 · Giyeong Heo, Younghwan Chang, et al. · IEEE Custom Integrated Circuits Conference (CICC) · 2
Energy-Efficient Dynamic Comparator with Active Inductor for Receiver of Memory Interfaces
2018 · Jae Whan Lee, Joo-Hyung Chae, et al. · International Symposium on Low Power Electronics and Design (ISLPED) · 2
A Fully Integrated 16-MHz Voltage-Mode Relaxation Oscillator With Current Calibration for Temperature Compensation
2026 · Jaekwang Yun, Jooyeol Rhee · IEEE Transactions on Circuits & Systems II Express Briefs · 1
MTA-Coded PAM-4 Receiver with Decision Feedback Power Saving Scheme and Partial DFE for Low-Power Memory Interfaces
2025 · Jusung Lee, Younghwan Chang, et al. · IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) · 1
Energy-Efficient Single-Ended Capacitive PAM-4 Transceiver for Next-Generation HBM Interfaces
2025 · Jaeyoon Kim, Sangyoon Lee, et al. · IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) · 1
A 0.77-pJ/bit 40-Gb/s/pin Single-Ended Hybrid DAC-Based Transmitter for Memory Interfaces
2024 · Sanghyuk Seo, Yong-un Jeong, et al. · IEEE International Symposium on Circuits and Systems proceedings · 1
A Wideband Fractional-N PLL with Transition-Detection DAC for SDM-Based Quantization Noise Cancellation in Precision Timing Measurement
2026 · Chan-Ho Kye, Jaekwang Yun · Electronics
A 0.53-pJ/bit 5 × 10 Gb/s/pin Single-Ended Transceiver With Reconfigurable 4-Aggressor Crosstalk Cancellation for HBM Interfaces
2026 · Sanghyuk Seo, Suhwan Kim, et al. · IEEE Transactions on Circuits and Systems I Regular Papers
A Single-Ended MTA PAM-4 Receiver With Analog-Front-End Nonlinearity Compensation Using MTA-Error Correction Scheme for Memory Interfaces
2026 · Sanghyuk Seo, Jusung Lee, et al. · IEEE Access
A 19.8-Gb/s/Wire Single-Ended PAM-3/NRZ Simultaneous Bidirectional Transceiver With Shared ZQ/Hybrid Calibration for Memory Interfaces
2026 · Jusung Lee, Sanghyuk Seo, et al. · IEEE Transactions on Circuits and Systems I Regular Papers
A 0.38-pJ/bit 35-Gb/s/pin Single-Ended Impedance-Matched PAM-4 Transmitter with CML-Assisted N-over-N Driver for Memory Interfaces
2026 · Jusung Lee, Sanghyuk Seo, et al. · IEEE Transactions on Circuits & Systems II Express Briefs
A Bridge IC With Programmable DQS/WCK Pattern Generation and RDQS Error Detection for Next-Generation Mobile Memory Interface Testing
2026 · Jaekwang Yun, Chan-Ho Kye · IEEE Access
A Single-Ended Transmitter With Asymmetric Voltage- and Time-Domain Crosstalk Cancellation for Low-Power Memory Interfaces
2026 · Jaekwang Yun, Yong-Un Jeong · IEEE Transactions on Circuits and Systems I Regular Papers
A 24-Gb/s/pin Single-Ended PAM-3 Transmitter With 8-bit/6-UI Encoding based partial-MTA for Low-Power Memory Interfaces
2025 · Jaeyoon Kim, Sanghyuk Seo, et al. · IEEE Asian Solid-State Circuits Conference (A-SSCC)
Works count: 25
Citation count: 99
H-index: 7
I10-index: 5
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