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Author

Tanushree Ganguli

Observed name: Tanushree Ganguly
ORCID: 0009-0005-7542-4996
Observed ORCID: 0009-0005-7542-4996
OpenAlex ID: A5016076782
Impact of Interface Trap Charges on the Performances of Junctionless MOSFET in Sub-Threshold Regime
2022 · Tanushree Ganguli, Manash Chanda, et al. · Computers & Electrical Engineering · 27
Energy Efficient Adiabatic Logic Styles in Sub-Threshold Region for Ultra Low Power Application
2017 · Manash Chanda, Tanushree Ganguli, et al. · Journal of Low Power Electronics · 11
Impact of Aspect Ratio and Interface Trap Charge on the Performances of Junctionless MOSFET-Based Adiabatic Logic Circuit
2023 · Tanushree Ganguli, Manash Chanda, et al. · IEEE Transactions on Electron Devices · 7
Analysis of Double-Gate Junctionless MOSFET for Energy Efficient Digital Application
2021 · Adrija Mukherjee, Deepro Banerjee, et al. · Devices for Integrated Circuit (DevIC) · 4
Design and analysis of adiabatic complex sequential logic circuits in sub-threshold regime for ultra-low power application
2016 · Manash Chanda, Diptansu Sinha, et al. · International Conference on Communications and Signal Processing (ICCSP) · 3
Design and implementation of adiabatic multiplier in sub-threshold regime for ultra low power application
2016 · Manash Chanda, Jeet Basak, et al. · International Conference on Communications and Signal Processing (ICCSP) · 3
Comparative analysis of adiabatic logics in sub-threshold regime for ultra-low power application
2016 · Manash Chanda, Jeet Basak, et al. · Conference on Emerging Devices and Smart Systems (ICEDSS) · 2
Junctionless MOSFET-based Adiabatic Adder for Energy-Efficient Application
2026 · Tanushree Ganguly, Foyjun De, et al. · Journal of Integrated Circuits and Systems
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An Energy-Efficient 16-Bit Edge AI Architecture Featuring a Systolic Array with Adaptive Vedic Multipliers
2026 · Subhadip Ghanta, Tanushree Ganguly, et al. · International Conference on Signal Analysis for Smart Systems (SIGNASS)
Comparative Analysis of Vedic, Booth, Dadda, and Array Multiplier Architectures for Processing Elements in a Systolic Array-Based Edge AI Architecture
2026 · Subhadip Ghanta, Adwitiyo Bera, et al. · International Conference on Computing, Electronics & Communications Engineering (iCCECE)
Impact of the Threshold Voltage Variability of the Junctionless MOSFET on Digital Performances in Sub-threshold Regime
2025 · Tanushree Ganguli, Sristi Das, et al. · Devices for Integrated Circuit (DevIC)
Design and analysis of adiabatic logic in sub-threshold regime for ultra low power application
2016 · Manash Chanda, Diptansu Sinha, et al. · Conference on Emerging Devices and Smart Systems (ICEDSS)
Works count: 12
Citation count: 57
H-index: 4
I10-index: 2
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