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Veerle Derudder

Observed names: Derudder, Veerle, V. Derudder
Observed institutions: IMEC, KU Leuven
ORCID: 0000-0002-5596-9471
Observed ORCID: 0000-0002-5596-9471
OpenAlex ID: A5017562184
A new algorithm for elimination of common subexpressions
1999 · R. Pasko, P. Schaumont, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 293
A 79-GHz 2 $\times $ 2 MIMO PMCW Radar SoC in 28-nm CMOS
2017 · Davide Guermandi, Qixian Shi, et al. · IEEE Journal of Solid-State Circuits · 168
A performance and complexity comparison of auto-correlation and cross-correlation for OFDM burst synchronization
2003 · A. Fort, J.-W. Weijers, et al. · IEEE International Conference on Acoustics Speech and Signal Processing · 79
A scalable 8.7nJ/bit 75.6Mb/s parallel concatenated convolutional (turbo-) CODEC
2003 · B. Bougard, A. Giulietti, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 59
80-Mb/s QPSK and 72-Mb/s 64-QAM flexible and scalable digital OFDM transceiver ASICs for wireless local area networks in the 5-GHz band
2001 · W. Eberle, V. Derudder, et al. · IEEE Journal of Solid-State Circuits · 52
High-Speed LDPC Decoders Towards 1 Tb/s
2021 · Meng Li, Veerle Derudder, et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 48
A 200Mbps+ 2.14 nJ/b digital baseband multi processor system-on-chip for SDRs
2009 · Derudder, Veerle, Bougard, Bruno, et al. · HAL · 35
A 10.37 mm2 675 mW reconfigurable LDPC and Turbo encoder and decoder for 802.11n, 802.16e and 3GPP-LTE
2010 · F. Naessens, V. Derudder, et al. · Symposium on VLSI Circuits · 29
Mapping a multiple antenna SDM-OFDM receiver on the ADRES coarse-grained reconfigurable processor
2006 · D. Novo, W. Moffat, et al. · SiPS ... design and implementation - IEEE Workshop on Signal Processing Systems · 29
A 80 Mb/s low-power scalable turbo codec core
2003 · A. Giulietti, B. Bougard, et al. · Custom Integrated Circuits Conference · 28
4.1 A 16GHz, $41\text{kHz}_{\text{rms}}$ Frequency Error, Background-Calibrated, Duty-Cycled FMCW Charge-Pump PLL
2023 · Pratap Tumkur Renukaswamy, Kristof Vaesen, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 26
An energy efficient 18Gbps LDPC decoding processor for 802.11ad in 28nm CMOS
2015 · Meng Li, Jan-Willem Weijers, et al. · IEEE Asian Solid-State Circuits Conference (A-SSCC) · 22
A digital 80 Mb/s OFDM transceiver IC for wireless LAN in the 5 GHz band
2002 · W. Eberle, M. Badaroglu, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 22
A digital 72 Mb/s 64-QAM OFDM transceiver for 5 GHz wireless LAN in 0.18 μm CMOS
2002 · W. Eberle, V. Derudder, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 17
A 79GHz 2×2 MIMO PMCW radar SoC in 28nm CMOS
2016 · D. Guermandi, Q. Shi, et al. · IEEE Asian Solid-State Circuits Conference (A-SSCC) · 15
From MIMO-OFDM Algorithms to a Real-Time Wireless Prototype: A Systematic Matlab-to-Hardware Design Flow
2006 · Jan-Willem Weijers, Veerle Derudder, et al. · EURASIP Journal on Advances in Signal Processing · 15
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An integrated reconfigurable engine for multi-purpose sensing up to 6 GHz
2011 · Sofie Pollin, Lieven Hollevoet, et al. · IEEE International Symposium on Dynamic Spectrum Access Networks · 14
Optimization method for broadband modem FIR filter design using common subexpression elimination
1997 · R. Pasko, Patrick Schaumont, et al. · 13
A 100 Gbps LDPC Decoder for the IEEE 802.11ay Standard
2018 · Meng Li, Veerle Derudder, et al. · International Symposium on Turbo Codes and Iterative Information Processing · 12
Tb/s Polar Successive Cancellation Decoder 16nm ASIC Implementation
2020 · Süral, Altuğ, Sezer, E. Göksu, et al. · arXiv (Cornell University) · 11
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Flexible OFDM transceiver for a high-speed wireless LAN
2003 · W. Eberle, M. Badaroglu, et al. · IEEE Vehicular Technology Conference · 11
Memory power reduction for the highspeed implementation of turbo codes
2002 · F. Maessen, A. Giulietti, et al. · SiPS ... design and implementation - IEEE Workshop on Signal Processing Systems · 10
Optimization method for broadband modem FIR filter design using common subexpression elimination
2002 · R. Pasko, P. Schaumont, et al. · International Symposium on System Synthesis (ISSS) · 9
Subword-Parallel VLIW Architecture Exploration for Multimode Software Defined Radio
2006 · T. Schuster, D. Novo Bruna, et al. · SiPS ... design and implementation - IEEE Workshop on Signal Processing Systems · 7
An approach for real time prototyping of MIMO-OFDM systems
2004 · Maryse Wouters, André Bourdoux, et al. · 7
Works count: 33
Citation count: 1,042
H-index: 15
I10-index: 22
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