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Pieter Schuddinck

Observed names: P Schuddinck, P. Schuddinck
Institution: IMEC
Observed institutions: IMEC, KU Leuven
OpenAlex ID: A5017651762
Device Exploration of NanoSheet Transistors for Sub-7-nm Technology Node
2017 · Doyoung Jang, Dmitry Yakimets, et al. · IEEE Transactions on Electron Devices · 298
The Complementary FET (CFET) for CMOS scaling beyond N3
2018 · J. Ryckaert, P. Schuddinck, et al. · Symposium on VLSI Technology · 276
Vertical GAAFETs for the Ultimate CMOS Scaling
2015 · Dmitry Yakimets, Geert Eneman, et al. · IEEE Transactions on Electron Devices · 211
First Monolithic Integration of 3D Complementary FET (CFET) on 300mm Wafers
2020 · S. Subramanian, M. Hosseini, et al. · Symposium on VLSI Technology · 141
Understanding Energy Efficiency Benefits of Carbon Nanotube Field-Effect Transistors for Digital VLSI
2018 · Gage Hills, Marie Garcia Bardon, et al. · IEEE Transactions on Nanotechnology · 138
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Power aware FinFET and lateral nanosheet FET targeting for 3nm CMOS technology
2017 · D. Yakimets, M. Garcia Bardon, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 119
Novel forksheet device architecture as ultimate logic scaling device towards 2nm
2019 · P. Weckx, J. Ryckaert, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 115
Enabling Sub-5nm CMOS Technology Scaling Thinner and Taller!
2019 · J. Ryckaert, M. H. Na, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 98
Device-, Circuit- & Block-level evaluation of CFET in a 4 track library
2019 · P. Schuddinck, O. Zografos, et al. · Symposium on VLSI Technology · 74
Extreme scaling enabled by 5 tracks cells: Holistic design-device co-optimization for FinFETs and lateral nanowires
2016 · M. Garcia Bardon, Y. Sherazi, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 74
PPAC of sheet-based CFET configurations for 4 track design with 16nm metal pitch
2022 · P. Schuddinck, F. M. Bufler, et al. · IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 71
A Comprehensive Study of Nanosheet and Forksheet SRAM for Beyond N5 Node
2021 · Mohit Kumar Gupta, Pieter Weckx, et al. · IEEE Transactions on Electron Devices · 58
CFET SRAM DTCO, Interconnect Guideline, and Benchmark for CMOS Scaling
2023 · Hsiao-Hsuan Liu, Shairfe M. Salahuddin, et al. · IEEE Transactions on Electron Devices · 55
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Power-performance Trade-offs for Lateral NanoSheets on Ultra-Scaled Standard Cells
2018 · M. Garcia Bardon, Y. Sherazi, et al. · Symposium on VLSI Technology · 54
Dimensioning for power and performance under 10nm: The limits of FinFETs scaling
2015 · M. Garcia Bardon, P. Schuddinck, et al. · IEEE International Conference on IC Design and Technology (ICICDT) · 54
Stacked nanosheet fork architecture for SRAM design and device co-optimization toward 3nm
2017 · P. Weckx, J. Ryckaert, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 52
Vertical device architecture for 5nm and beyond: Device & circuit implications
2015 · A. V-Y Thean, D. Yakimets, et al. · Symposium on VLSI Technology · 52
Introducing 2D-FETs in Device Scaling Roadmap using DTCO
2020 · Z. Ahmed, A. Afzalian, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 50
The Complementary FET (CFET) 6T-SRAM
2021 · Mohit Kumar Gupta, Pieter Weckx, et al. · IEEE Transactions on Electron Devices · 47
Holisitic device exploration for 7nm node
2015 · P. Raghavan, M. Garcia Bardon, et al. · Custom Integrated Circuits Conference · 46
PPA and Scaling Potential of Backside Power Options in N2 and A14 Nanosheet Technology
2023 · S. Yang, P. Schuddinck, et al. · IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 45
Limitations on Lateral Nanowire Scaling Beyond 7-nm Node
2016 · Uttam Kumar Das, M. Garcia Bardon, et al. · IEEE Electron Device Letters · 41
CFET SRAM With Double-Sided Interconnect Design and DTCO Benchmark
2023 · Hsiao-Hsuan Liu, Pieter Schuddinck, et al. · IEEE Transactions on Electron Devices · 38
DTCO at N7 and beyond: patterning and electrical compromises and opportunities
2015 · Julien Ryckaert, Praveen Raghavan, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 32
Layout-induced stress effects in 14nm & 10nm FinFETs and their impact on performance
2013 · M. Garcia Bardon, Victor Moroz, et al. · Symposium on VLSI Circuits · 28
Works count: 63
Citation count: 2,634
H-index: 26
I10-index: 41
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