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Koichi Hamashita

Observed names: K Hamashita, K. Hamashita, Koichi HAMASHITA
OpenAlex ID: A5018272165
Ring Amplifiers for Switched Capacitor Circuits
2012 · Benjamin Hershberg, Skyler Weaver, et al. · IEEE Journal of Solid-State Circuits · 245
A 0.6-V 82-dB delta-sigma audio ADC using switched-RC integrators
2005 · Gil-Cho Ahn, Dong-Young Chang, et al. · IEEE Journal of Solid-State Circuits · 87
A 10-mW 16-b 15-MS/s Two-Step SAR ADC With 95-dB DR Using Dual-Deadzone Ring Amplifier
2019 · Ahmed ElShater, Praveen Kumar Venkatachala, et al. · IEEE Journal of Solid-State Circuits · 73
A Stereo 16-Bit Delta-Sigma A/D Converter for Digital Audio
1989 · D.R. Welland, Bruce P. Del Signore, et al. · Journal of the Audio Engineering Society · 71
A Noise-Coupled Time-Interleaved Delta-Sigma ADC With 4.2 MHz Bandwidth, ${-}$98 dB THD, and 79 dB SNDR
2008 · Kyehyung Lee, Jeongseok Chae, et al. · IEEE Journal of Solid-State Circuits · 69
An 11-Bit 250-nW 10-kS/s SAR ADC With Doubled Input Range for Biomedical Applications
2017 · Mahmoud Sadollahi, Koichi Hamashita, et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 62
LMS-Based Noise Leakage Calibration of Cascaded Continuous-Time $\Delta\Sigma$ Modulators
2010 · Yun-Shiang Shu, Junpei Kamiishi, et al. · IEEE Journal of Solid-State Circuits · 57
Ring amplifiers for switched-capacitor circuits
2012 · Benjamin Hershberg, Skyler Weaver, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 54
Design of a 79 dB 80 MHz 8X-OSR Hybrid Delta-Sigma/Pipelined ADC
2010 · Omid Rajaee, Tawfiq Musah, et al. · IEEE Journal of Solid-State Circuits · 36
A 0.8 V, 2.6 mW, 88 dB Dual-Channel Audio Delta-Sigma D/A Converter With Headphone Driver
2009 · Kyehyung Lee, Qingdong Meng, et al. · IEEE Journal of Solid-State Circuits · 36
A Low Power Pipelined ADC Using Capacitor and Opamp Sharing Technique With a Scheme to Cancel the Effect of Signal Dependent Kickback
2009 · Naga Sasidhar, Youn-Jae Kook, et al. · IEEE Journal of Solid-State Circuits · 33
A 14b 60 MS/s Pipelined ADC Adaptively Cancelling Opamp Gain and Nonlinearity
2014 · Yuichi Miyahara, Mitsuhiro Sano, et al. · IEEE Journal of Solid-State Circuits · 32
A fifth-order gm–c continuous-time Δ Σ modulator with process-insensitive input linear range
2009 · Yusuke Aiba, Koji Tomioka, et al. · IEEE Journal of Solid-State Circuits · 28
A Hybrid Continuous-Time Incremental and SAR Two-Step ADC With 90.5-dB DR Over 1-MHz BW
2022 · Yanchao Wang, Siladitya Dey, et al. · IEEE Solid-State Circuits Letters · 26
3.7 A 10mW 16b 15MS/s Two-Step SAR ADC with 95dB DR Using Dual-Deadzone Ring-Amplifier
2019 · Ahmed ElShater, Calvin Yoji Lee, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 24
Adaptive cancellation of gain and nonlinearity errors in pipelined ADCs
2013 · Y. Miyahara, M. Sano, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 23
A 61.5dB SNDR pipelined ADC using simple highly-scalable ring amplifiers
2012 · Benjamin Hershberg, Skyler Weaver, et al. · Symposium on VLSI Circuits · 23
Low-OSR Over-Ranging Hybrid ADC Incorporating Noise-Shaped Two-Step Quantizer
2011 · Omid Rajaee, Seiji Takeuchi, et al. · IEEE Journal of Solid-State Circuits · 23
An Oversampling Stochastic ADC Using VCO-Based Quantizers
2018 · Hyuk Sun, Kazuki Sobue, et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 21
A Noise-Coupled Time-Interleaved ¿¿ ADC with 4.2MHz BW, -98dB THD, and 79dB SNDR
2008 · Kyehyung Lee, Jeongseok Chae, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 21
A 16b 1.62MS/s Calibration-free SAR ADC with 86.6dB SNDR utilizing DAC Mismatch Cancellation Based on Symmetry
2020 · Shota Konno, Yuichi Miyahara, et al. · IEEE Asian Solid-State Circuits Conference (A-SSCC) · 16
A 1.25MS/S Two-Step Incremental ADC with 100DB DR and 110DB SFDR
2018 · Takato Katayama, Shiko Miyashita, et al. · Symposium on VLSI Circuits · 15
A two-capacitor SAR-assisted multi-step incremental ADC with a single amplifier achieving 96.6 dB SNDR over 1.2 kHz BW
2017 · Yi Zhang, Chia-Hung Chen, et al. · Custom Integrated Circuits Conference · 14
A 951-fsrms Period Jitter 3.2% Modulation Range in-Band Modulation Spread-Spectrum Clock Generator
2019 · Hyuk Sun, Kazuki Sobue, et al. · IEEE Journal of Solid-State Circuits · 13
A 1.25 MS/s Two-Step Incremental ADC With 100-dB DR and 110-dB SFDR
2018 · Takato Katayama, Shiko Miyashita, et al. · IEEE Solid-State Circuits Letters · 13
Works count: 48
Citation count: 1,218
H-index: 20
I10-index: 28
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