Author

Enrique Alvarez-Fontecilla

Observed names: E. Alvarez-Fontecilla, Enrique Alvarez Fontecilla, Enrique Álvarez Fontecilla

Institution: Analog Devices (United States)

Observed institutions: Analog Devices (United States), Pontificia Universidad Católica de Chile, University of California San Diego

ORCID: 0000-0002-2446-0445

Observed ORCID: 0000-0002-2446-0445

OpenAlex ID: A5018941756

High-Density Redox Amplified Coulostatic Discharge-Based Biosensor Array

2018 · Alexander C. Sun, Enrique Alvarez-Fontecilla, et al. · IEEE Journal of Solid-State Circuits · 25

Optimal CCD readout by digital correlated double sampling

2015 · C. Alessandri, A. Abusleme, et al. · Monthly Notices of the Royal Astronomical Society · 21

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A Time Amplifier Assisted Frequency-to-Digital Converter Based Digital Fractional-N PLL

2021 · Eslam Helal, Enrique Alvarez-Fontecilla, et al. · IEEE Journal of Solid-State Circuits · 14

Canonical Syllogistic Moods in Traditional Aristotelian Logic

2016 · Enrique Alvarez-Fontecilla · Logica Universalis · 11

Understanding High-Resolution Dynamic Element Matching DACs [Feature]

2023 · Enrique Alvarez-Fontecilla, Paul S. Wilkins, et al. · IEEE Circuits and Systems Magazine · 8

Delta-Sigma FDC Enhancements for FDC-Based Digital Fractional-N PLLs

2020 · Enrique Alvarez-Fontecilla, Amr I. Eissa, et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 7

24.8 A 12GS/s 9b 16× Time-Interleaved SAR ADC in 16nm FinFET

2025 · Junhua Shen, Wei-Hung Chen, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 6

Aristotelian Logic Axioms in Propositional Logic: The Pouch Method

2018 · Enrique Alvarez-Fontecilla, Tomas Lungenstrass · History and Philosophy of Logic · 5

A 64×64 high-density redox amplified coulostatic discharge-based biosensor array in 180nm CMOS

2017 · Alexander Sun, Enrique Alvarez-Fontecilla, et al. · European Solid-State Circuits Conference (ESSCIRC) · 5

Multi-Rate DEM With Mismatch-Noise Cancellation for DCOs in Digital PLLs

2018 · Enrique Alvarez-Fontecilla, Christian Venerus, et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 4

A 12b 12GS/s Two-Way Interleaved Pipeline ADC with Integrated Broadband RF VGA in 5nm

2026 · Haiyang Zhu, Larry Singer, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 2

Linearity Through Democracy [Feature]

2025 · Enrique Alvarez-Fontecilla, Paul S. Wilkins · IEEE Circuits and Systems Magazine · 2

Spectral Breathing and Its Mitigation in Digital Fractional-N PLLs

2021 · Enrique Alvarez-Fontecilla, Eslam Helal, et al. · IEEE Journal of Solid-State Circuits · 2

A Non-Linearity Compensation Technique for Charge-Redistribution SAR ADCs

2019 · Enrique Alvarez-Fontecilla, Angel Abusleme · IEEE Latin American Test Symposium (LATS) · 2

Passive reference-sharing SAR ADC

2015 · Enrique Alvarez-Fontecilla, Angel Abusleme · Microelectronics Journal · 2

A Duty-Cycle-Error-Immune Reference Frequency Doubling Technique for Fractional-N Digital PLLs

2024 · Amr I. Eissa, Enrique Alvarez-Fontecilla, et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 1

FunDEMentals of Error-Shaping DEM DACs [Feature]

2026 · Enrique Alvarez-Fontecilla, Paul S. Wilkins · IEEE Circuits and Systems Magazine

CMOS techniques in integrated circuits for particle physics experiments

2013 · Enrique Álvarez Fontecilla

Works count: 18

Citation count: 117

H-index: 6

I10-index: 4