Product
Help
Pricing
About
Jobs
Log in
Get started
Author
Add to collection
Shobhit Malik
Institution:
GlobalFoundries (United States)
Observed institution:
GlobalFoundries (United States)
OpenAlex ID:
A5019291470
Framework for identifying recommended rules and DFM scoring model to improve manufacturability of sub-20nm layout design
2012
·
Piyush Pathak
, Sriram Madhavan
, et al.
·
Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE
·
11
Automated yield enhancements implementation on full 28nm chip: challenges and statistics
2012
·
Shobhit Malik
, Sriram Madhavan
, et al.
·
Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE
·
3
Quantifying electrical impacts on redundant wire insertion in 7nm unidirectional designs
2017
·
Ahmed Mohyeldin
, Uwe Paul Schroeder
, et al.
·
Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE
·
2
Deriving Feature Fail Rate from Silicon Volume Diagnostics Data
2013
·
Shobhit Malik
, Thomas Herrmann
, et al.
·
IEEE Design and Test
·
2
Yield enhancement flow for analog and full custom designs reliability-rules automatic application
2011
·
Ahmad Abdulghany
, Rami Fathy
, et al.
·
International Design and Test Workshop (IDT)
·
2
Enhanced layout optimization of sub-45nm standard: memory cells and its effects
2009
·
Seung Weon Paek
, Dae Hyun Jang
, et al.
·
Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE
·
2
Quick Yield Impact Assessment Using Silicon-design Correlation to Address Design Systematics
2021
·
Chenlong Miao
, Deborah Ryan
, et al.
·
ASMC proceedings
·
1
Fast, high-capacity critical area analysis (CAA) with advanced FINFET defectivity calculation
2021
·
Xiaoyuan Qi
, Atul Chittora
, et al.
·
SPIE Design-Process-Technology Co-optimization
·
1
Foundry approach for layout risk assessment through comprehensive pattern harvesting and large-scale data analysis
2020
·
Monisa Ramesh Babu
, Shenghua Song
, et al.
·
Design-Process-Technology Co-optimization for Manufacturability
·
1
CAPP: context analyzer and printability predictor
2019
·
Vikas Tripathi
, Yongfu Li
, et al.
·
Design-Process-Technology Co-optimization for Manufacturability
·
1
Quantified contribution of design for manufacturing to yield at 28nm
2014
·
Thomas Herrmann
, Shobhit Malik
, et al.
·
IEEE European Test Symposium (ETS)
·
1
Decomposition-aware layout optimization for 20/14nm standard cells
2014
·
Lynn T. -. Wang
, Sriram Madhavan
, et al.
·
Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE
·
1
A scoring methodology for quantitatively evaluating the quality of double patterning technology-compliant layouts
2012
·
Lynn T. Wang
, Sriram Madhavan
, et al.
·
Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE
·
1
Methodologies to handle large volumes of design and defect data for improved pre-silicon defect prediction
2022
·
Parnashri Wankhede
, Devansh Singh
, et al.
·
DTCO and Computational Patterning
Fault Isolation using Layout Pattern Analysis
2020
·
Atul Chittora
, Neerja Bawaskar
, et al.
·
Proceedings - International Symposium for Testing and Failure Analysis
DiagBridge: Analyzing scan diagnosis data in a yield perspective
2014
·
Yan Pan
, Atul Chittora
, et al.
·
ASMC proceedings
Smart double-cut via insertion flow with dynamic design-rules compliance for fast new technology adoption
2012
·
Ahmad Abdulghany
, Rami Fathy
, et al.
·
Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE
Show more works
View as search
Works count:
17
Citation count:
29
H-index:
2
I10-index:
1
Year
Topic
Type
