Author

Bingfeng Mei

Observed names: B. Mei, Bing-Feng Mei

Institution: IMEC

Observed institutions: IMEC, KU Leuven

OpenAlex ID: A5019368065

ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix

2003 · Bingfeng Mei, Serge Vernalde, et al. · Lecture notes in computer science · 572

DRESC: a retargetable compiler for coarse-grained reconfigurable architectures

2003 · Bingfeng Mei, S. Vernalde, et al. · International Conference on Field-Programmable Technology (FPT) · 214

Exploiting loop-level parallelism on coarse-grained reconfigurable architectures using modulo scheduling

2003 · B. Mei, S. Vernalde, et al. · IEE Proceedings - Computers and Digital Techniques · 212

Architecture Exploration for a Reconfigurable Architecture Template

2005 · Bingfeng Mei, A. Lambrechts, et al. · IEEE Design & Test of Computers · 171

Design methodology for a tightly coupled VLIW/reconfigurable matrix architecture: a case study

2004 · Bingfeng Mei, Serge Vernalde, et al. · 139

Exploiting loop-level parallelism on coarse-grained reconfigurable architectures using modulo scheduling

2003 · Bingfeng Mei, S. Vernalde, et al. · Design, Automation, and Test in Europe · 116

Custom implementation of the coarse-grained reconfigurable ADRES architecture for multimedia purposes

2005 · F. Veredas, M. Scheppler, et al. · International Conference on Field Programmable Logic and Applications (FPL) · 94

Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder

2007 · B. Mei, B. De Sutter, et al. · Journal of Signal Processing Systems · 63

Mapping an H.264/AVC decoder onto the ADRES reconfigurable architecture

2005 · Bingfeng Mei, F.-J. Veredas, et al. · International Conference on Field Programmable Logic and Applications (FPL) · 47

ADRES & DRESC: Architecture and Compiler for Coarse-Grain Reconfigurable Processors

2007 · B. Mei, M. Berekovic, et al. · Springer eBooks · 37

Placement-and-routing-based register allocation for coarse-grained reconfigurable arrays

2008 · Bjorn De Sutter, Paul Coene, et al. · ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES) · 30

Placement-and-routing-based register allocation for coarse-grained reconfigurable arrays

2008 · Bjorn De Sutter, Paul Coene, et al. · ACM SIGPLAN Notices · 16

Interconnect Exploration for Energy Versus Performance Tradeoffs for Coarse Grained Reconfigurable Architectures

2008 · A. Lambrechts, P. Raghavan, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 14

Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardware

2001 · Yajun Ha, Bingfeng Mei, et al. · Lecture notes in computer science · 13

An Efficient Memory Organization for High-ILP Inner Modem Baseband SDR Processors

2009 · Bjorn De Sutter, Osman Allam, et al. · Journal of Signal Processing Systems · 9

Mapping of nomadic multimedia applications on the ADRES reconfigurable array processor

2009 · Mladen Berekovic, Andreas Kanstein, et al. · Microprocessors and Microsystems · 6

Design Style Case Study for Embedded Multi Media Compute Nodes

2005 · A. Lambrechts, T. Vander Aa, et al. · IEEE Real-Time Systems Symposium (RTSS) · 6

Interconnect architectures for modulo-scheduled coarse-grained reconfigurable arrays

2005 · S.J.E. Wilton, N. Kafafi, et al. · International Conference on Field-Programmable Technology (FPT) · 6

A backtracking instruction scheduler using predicate-based code hoisting to fill delay slots

2007 · Tom Vander Aa, Bing-Feng Mei, et al. · International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES) · 5

Design and optimization of dynamically reconfigurable embedded systems

2001 · Bingfeng Mei, Serge Vernalde, et al. · 4

Hardware and a Tool Chain for ADRES

2006 · Bjorn De Sutter, Bingfeng Mei, et al. · Lecture notes in computer science · 3

Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardware

2007 · Yajun Ha, Bingfeng Mei, et al. · 1

A Tightly Coupled VLIW/Reconfigurable Matrix and its Modulo Scheduling Technique

2005 · Bingfeng Mei, Serge Vernalde, et al. · Springer eBooks

Energy aware architecture exploration of a CGRA template

2005 · Andy Lambrechts, Praveen Raghavan, et al.

Design style case study for computer nodes of a heterogeneous NoC platform

2004 · Andy Lambrechts, Tom Vander Aa, et al.

Works count: 25

Citation count: 1,778

H-index: 13

I10-index: 14