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Masanori Hayashikoshi

Observed names: Hayashikoshi Masanori, Hayashikoshi, Masanori, M. Hayashikoshi, Masanori HAYASHIKOSHI
ORCID: 0000-0002-1962-4708
Observed ORCID: 0000-0002-1962-4708
OpenAlex ID: A5019515253
A high-density and high-speed 1T-4MTJ MRAM with Voltage Offset Self-Reference Sensing Scheme
2006 · Hiroaki Tanizaki, Takaharu Tsuji, et al. · IEEE Asian Solid-State Circuits Conference (A-SSCC) · 35
A 34-ns 16-Mb DRAM with controllable voltage down-converter
1992 · H. Hidaka, K. Arimoto, et al. · IEEE Journal of Solid-State Circuits · 25
Normally-off MCU architecture for low-power sensor node
2014 · Masanori Hayashikoshi, Yohei Sato, et al. · Asia and South Pacific Design Automation Conference (ASP-DAC) · 23
Low-Power Multi-Sensor System with Power Management and Nonvolatile Memory Access Control for IoT Applications
2018 · Masanori Hayashikoshi, Hideyuki Noda, et al. · IEEE Transactions on Multi-Scale Computing Systems · 11
Processing In-Memory Architecture with On-Chip Transfer Learning Function for Compensating Characteristic Variation
2020 · Masanori Hayashikoshi, Junichi Suzuki, et al. · IEEE International Memory Workshop (IMW) · 8
Design Aid of Multi-core Embedded Systems with Energy Model
2014 · Takashi Nakada, Kazuya Okamoto, et al. · IPSJ Online Transactions · 8
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A high-speed parallel sensing architecture for multi-megabit flash E/sup 2/PROMs
1990 · K. Kobayashi, T. Nakayama, et al. · IEEE Journal of Solid-State Circuits · 8
Low-power multi-sensor system with task scheduling and autonomous standby mode transition control for IoT applications
2017 · Masanori Hayashikoshi, Hideyuki Noda, et al. · IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) · 7
Energy-Efficient Continuous Task Scheduling for Near Real-Time Periodic Tasks
2015 · Takashi Nakada, Hiroyuki Yanagihashi, et al. · IEEE International Conference on Data Science and Data Intensive Systems · 7
Low-power multi-sensor system with normally-off sensing technology for IoT applications
2016 · Masanori Hayashikoshi, Hideyuki Noda, et al. · International SoC Design Conference · 6
An Energy-Efficient Task Scheduling for Near Real-Time Systems on Heterogeneous Multicore Processors
2020 · Takashi NAKADA, Hiroyuki YANAGIHASHI, et al. · IEICE Transactions on Information and Systems · 5
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Normally-off MCU architecture and power management method for low-power sensor network
2015 · Masanori Hayashikoshi, Hiroyuki Kawai, et al. · International SoC Design Conference · 5
120-ns 128 K*8-bit/64 K*16-bit CMOS EEPROMs
1989 · Y. Terada, K. Kobayashi, et al. · IEEE Journal of Solid-State Circuits · 5
A Cost-Effective High Accuracy Auto-Trimming System without Tester Constraint for Low-End Embedded Flash Memory
2018 · Junichi Suzuki, Junichi Yamashita, et al. · International SoC Design Conference · 3
Energy-aware task scheduling for near real-time periodic tasks on heterogeneous multicore processors
2017 · Takashi Nakada, Hiroyuki Yanagihashi, et al. · IFIP/IEEE International Conference on Very Large Scale Integration · 3
Non-volatile Memories
2017 · Koji Ando, Shinobu Fujita, et al. · Springer eBooks · 3
An adaptive energy-efficient task scheduling under execution time variation based on statistical analysis
2016 · Takashi Nakada, Tomoki Hatanaka, et al. · IFIP/IEEE International Conference on Very Large Scale Integration · 3
Data-aware power management for periodic real-time systems with non-volatile memory
2014 · Takashi Nakada, Takuya Shigematsu, et al. · IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA) · 3
A Cost-Effective 1T-4MTJ Embedded MRAM Architecture with Voltage Offset Self-Reference Sensing Scheme for IoT Applications
2019 · Masanori HAYASHIKOSHI, Hiroaki TANIZAKI, et al. · IEICE Transactions on Electronics · 2
Highly reliable testing of ULSI memories with on-chip voltage-down converters
1993 · M. Tsukude, K. Arimoto, et al. · IEEE Design & Test of Computers · 2
A 1Mb High-Density Toggle-MRAM with Symmetrical Read/Write Operations
2007 · Hiroaki Tanizaki, Takaharu Tsuji, et al. · IEEE International Memory Workshop (IMW) · 1
120 ns 128 k*8 b/64 k*16 b CMOS EEPROMs
2003 · Y. Terada, K. Kobayashi, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 1
A Dual-mode Sensing Scheme Of Capacitor Coupled EEPROM Cell For Super High Endurance
1991 · M. Hayashikoshi, H. Hidaka, et al. · Symposium on VLSI Circuits · 1
High speed page mode sensing scheme for EPROMs and flash EEEPROMs using divided bit line architecture
1990 · Y. Terada, T. Nakayama, et al. · Symposium on VLSI Circuits · 1
Research and Development of Normally-Off Computing—NEDO Project
2017 · Takashi Nakada, Shinobu Fujita, et al. · Springer eBooks
Works count: 35
Citation count: 176
H-index: 7
I10-index: 4
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