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D.S. Shylu Sam

Observed names: D S. Shylu Sam, D. D. Shylu Sam, D. S. Shylu Sam, D. Shylu Sam, D.S.Shylu Sam
Institution: Karunya University
Observed institution: Karunya University
ORCID: 0000-0001-5559-0202
Observed ORCID: 0000-0001-5559-0202
OpenAlex ID: A5020695863
Application of machine learning techniques for churn prediction in the telecom business
2024 · Raji Krishna, D. Jayanthi, et al. · Results in Engineering · 33
A Novel Architecture for 10-bit 40MSPS Low Power Pipelined ADC Using a Simultaneous Capacitor and Op-amp Sharing Technique
2021 · D.S.Shylu Sam, D. Jackuline Moni, et al. · Silicon · 11
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Malware Identification in Advanced Interconnects on SOC
2022 · Galle Sangeeth, D Jayanthi, et al. · International Virtual Conference on Power Engineering Computing and Control: Developments in Electric Vehicles and Energy Sector for Sustainable Future (PECCON) · 10
A 10-bit 200 MS/s pipelined ADC with parallel sampling and switched op-amp sharing technique
2021 · D.S. Shylu Sam, P. Sam Paul · Circuit World · 9
A Novel architecture of a Low Power Folded Cascode OTA in 180nm CMOS process
2021 · D. S. Shylu Sam, P. Sam Paul, et al. · International Conference on Advanced Computing and Communication Systems (ICACCS) · 8
Design of Low Power Pass Transistor Logic Based Adders for Multiplier in 90nm CMOS Process
2023 · Durai Balaji R, D.S. Shylu Sam, et al. · 7
Design and Analysis of Two Stage Op-Amp in 180nm CMOS Process
2024 · Smrithi V., D.S.Shylu Sam, et al. · International Conference on Devices, Circuits and Systems (ICDCS) · 6
Design of Low–power 4-bit Flash ADC Using Multiplexer Based Encoder in 90nm CMOS Process
2022 · D. S. Shylu Sam, P. Sam Paul, et al. · International Journal of Electronics and Telecommunications · 6
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Differential Voltage Controlled Ring VCO with No Feedback Loop Technique for Radio Frequency Applications
2024 · Persiya Gnana Golda D., D.S. Shylu Sam, et al. · International Conference on Devices, Circuits and Systems (ICDCS) · 5
Design of highly reusable interface for AHB verification module
2022 · Vignesh T Mahendra, D.S. Shylu Sam, et al. · International Conference on Devices, Circuits and Systems (ICDCS) · 5
Design of High Speed Time – Interleaved SAR Analog to Digital Converter
2022 · A Josephine Atchaya, D.S. Shylu Sam, et al. · International Conference on Devices, Circuits and Systems (ICDCS) · 5
Design of Low Power Dynamic Comparator for SAR ADC
2022 · A J Herinsha, D.S. Shylu Sam, et al. · International Conference on Devices, Circuits and Systems (ICDCS) · 5
Performance Analysis of Array Multiplier Using Low-Power 10T Full Adder
2018 · D. S. Shylu Sam, A. Christina Roseline · Smart innovation, systems and technologies · 5
Design of 32-bit RISC V using area efficient multiplier based on homogeneous hybrid adder
2023 · G. Sangeeth, D. Jayanthi, et al. · AIP conference proceedings · 4
A New Embedded Clock Gating Technique in 8- bit Synchronous Counter with Reduced Switching Activity for Clock Divider Circuit
2023 · D. S. Shylu Sam, P. Sam Paul, et al. · WSEAS Transactions on Circuits and Systems archive · 3
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Design and Analysis of Frequency Synthesizer for Implantable Cardioverter Defibrillator (ICD) in 90 NM Technology
2023 · Shaik Babafakruddin, G Manoj, et al. · 3
Scalable UART Verification using AHP VIP for Optimal Coverage
2025 · D. Shylu Sam, G. Nivetha, et al. · International Conference on Advancements in Electrical, Electronics, Communication, Computing and Automation (ICAECA) · 2
Verification of UART using AHB VIP with Maximum Coverage
2024 · Persiya Gnana Golda D, S. Percy Deborah, et al. · International Conference on Devices, Circuits and Systems (ICDCS) · 2
Design of High-Performance Carry Select Adder using Multiplexer based Logic in 90nm Technology
2023 · Kanugula John Wesly, Sompalli Rajesh, et al. · 2
A Novel low power 2-D to 3-D Array Priority Encoder using Split-Logic Technique for Data Path Applications
2022 · D. S. Shylu Sam, P. Sam Paul, et al. · WSEAS TRANSACTIONS ON SYSTEMS AND CONTROL · 2
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Design of Low Power Dynamic CMOS Comparator for 10 – Bit SAR ADC using 180nm Technology Node
2025 · Anugrah Hembram, D.S. Shylu Sam · International Conference on Emerging Research in Electronics, Computer Science and Technology (ICERECT) · 1
A New Architecture of 4-Bit Flash ADC with Strong ARM Latch Dynamic Comparator
2025 · Mekala Manjunatha Reddy, Bellam Tharun, et al. · IEEE International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA) · 1
Analysis of nano sheet field effect transistor based on performance under different temperature and doping concentrations for 12 nm device
2024 · Raji Krishna, D. Jayanthi, et al. · Micro and Nanostructures · 1
Design and Comparison of Low Power Consumption Binary and Quaternary Multipliers
2023 · D. S. Shylu Sam, P. Sam Paul, et al. · National Academy Science Letters · 1
A new architecture of Thermometer to Binary code encoder for 4 - bit FLASH ADC in 45nm CMOS process
2023 · D.S.Shylu Sam · PRZEGLĄD ELEKTROTECHNICZNY · 1
Works count: 34
Citation count: 140
H-index: 6
I10-index: 3
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