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Hyun Chul Sagong
Observed names:
H. C. Sagong,
H. Sagong,
H.C. Sagong,
Hyun-Chul Sagong,
Hyun-chul Sagong,
Hyunchul Sagong
show all 6
Institutions:
Tech University of Korea,
Korea Automotive Technology Institute,
Dankook University
Observed institutions:
Pohang University of Science and Technology,
Tech University of Korea,
Samsung (South Korea),
Korea Automotive Technology Institute,
Samsung Electronics (South Korea),
The University of Texas at Austin,
Dankook University
show all 7
ORCID:
0009-0003-0236-6698
Observed ORCID:
0009-0003-0236-6698
OpenAlex ID:
A5021180754
Systematical study of 14nm FinFET reliability: From device level stress to product HTOL
2015
·
Changze Liu
, Hyun-Chul Sagong
, et al.
·
IEEE International Reliability Physics Symposium proceedings
·
48
Reliability on Evolutionary FinFET CMOS Technology and Beyond
2020
·
Kihyun Choi
, Hyun Chul Sagong
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
30
A systematic study of gate dielectric TDDB in FinFET technology
2018
·
Hyunjin Kim
, Minjung Jin
, et al.
·
IEEE International Reliability Physics Symposium proceedings
·
29
Considering physical mechanisms and geometry dependencies in 14nm FinFET circuit aging and product validations
2015
·
S. W. Pae
, H. C. Sagong
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
29
Analytic Model of S/D Series Resistance in Trigate FinFETs With Polygonal Epitaxy
2013
·
Chang-Woo Sohn
, Chang Yong Kang
, et al.
·
IEEE Transactions on Electron Devices
·
25
Enhanced Reliability of 7-nm Process Technology Featuring EUV
2019
·
Kihyun Choi
, Hyewon Shim
, et al.
·
IEEE Transactions on Electron Devices
·
20
Device Design Guidelines for Nanoscale FinFETs in RF/Analog Applications
2012
·
Chang-Woo Sohn
, Chang Yong Kang
, et al.
·
IEEE Electron Device Letters
·
20
Modeling of FinFET Self-Heating Effects in multiple FinFET Technology Generations with implication for Transistor and Product Reliability
2018
·
H. C. Sagong
, K. Choi
, et al.
·
Symposium on VLSI Technology
·
19
Investigation of alpha-induced single event transient (SET) in 10 nm FinFET logic circuit
2018
·
Taiki Uemura
, Soonyoung Lee
, et al.
·
IEEE International Reliability Physics Symposium proceedings
·
16
Analysis of Abnormal Upturns in Capacitance–Voltage Characteristics for MOS Devices With High-$k$ Dielectrics
2011
·
Chang-Woo Sohn
, Hyun Chul Sagong
, et al.
·
IEEE Electron Device Letters
·
14
Experimental study on BTI variation impacts in SRAM based on high-k/metal gate FinFET: From transistor level Vth mismatch, cell level SNM to product level Vmin
2015
·
Changze Liu
, Hyeonwoo Nam
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
12
Interfacial-Layer-Driven Dielectric Degradation and Breakdown of HfSiON/SiON Gate Dielectric nMOSFETs
2011
·
Do-Young Choi
, Kyong Taek Lee
, et al.
·
IEEE Electron Device Letters
·
12
New insights into 10nm FinFET BTI and its variation considering the local layout effects
2017
·
Changze Liu
, Minjung Jin
, et al.
·
IEEE International Reliability Physics Symposium proceedings
·
11
Localized Layout Effect Related Reliability Approach in 8nm FinFETs Technology: From Transistor to Circuit
2019
·
Hai Jiang
, Hyunchul Sagong
, et al.
·
IEEE International Reliability Physics Symposium proceedings
·
10
Simple S/D Series Resistance Extraction Method Optimized for Nanowire FETs
2013
·
Ye-Ram Kim
, Chang-Ki Baek
, et al.
·
IEEE Electron Device Letters
·
10
Decomposition of Charge Loss Mechanisms in 3-D Nand Flash Memory: Impact of Cell Dimension via High-Temperature Long-Term Retention Characteristics
2024
·
Jounghun Park
, Gilsang Yoon
, et al.
·
IEEE Transactions on Electron Devices
·
9
Analysis of Failure Mechanism and Reliability Enhancement of Silicon Strain Gauge-Based Pressure Sensor for Automotive Applications
2024
·
Hyunchul Sagong
, Seongcheol Jeong
, et al.
·
Sensors
·
9
PDF
Enhanced Reliability of 7nm Process Technology featuring EUV
2019
·
Kihyun Choi
, Hyun Chul Sagong
, et al.
·
Symposium on VLSI Technology
·
9
Advanced Self-heating Model and Methodology for Layout Proximity Effect in FinFET Technology
2020
·
Hai Jiang
, Hyunchul Sagong
, et al.
·
IEEE International Reliability Physics Symposium proceedings
·
8
A New Physical $\hbox{1}/f$ Noise Model for Double-Stack High-$k$ Gate-Dielectric MOSFETs
2009
·
Seung Hyun Song
, Hyun-Sik Choi
, et al.
·
IEEE Electron Device Letters
·
8
Reliability of Advanced FinFET Technology Nodes Beyond Planar: Invited
2020
·
Hyun Chul Sagong
, Kihyun Choi
, et al.
·
IEEE Electron Devices Technology & Manufacturing Conference (EDTM)
·
7
Reliability Assessment of 10nm FinFET Process Technology
2018
·
Jin Ju Kim
, Minjung Jin
, et al.
·
IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)
·
7
Comprehensive Hammering and Parasitic BJT Effects in Vertically Stacked DRAM
2024
·
Minki Suh
, Minsang Ryu
, et al.
·
IEEE Access
·
6
Effects of Far-BEOL anneal on the WLR and product reliability characterization of FinFET process technology
2018
·
Hyun Chul Sagong
, Hyunjin Kim
, et al.
·
IEEE International Reliability Physics Symposium proceedings
·
6
Comparative study of geometry-dependent capacitances of planar FETs and double-gate FinFETs: Optimization and process variation
2012
·
Chang-Woo Sohn
, Chang Yong Kang
, et al.
·
International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)
·
6
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Works count:
69
Citation count:
441
H-index:
12
I10-index:
15
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