Product
Help
Pricing
About
Jobs
Log in
Get started
Author
Add to collection
Avinash Lahgere
Observed names:
A. Lahgere,
Lahgere, Avinash
Institution:
Indian Institute of Technology Kanpur
Observed institutions:
Indian Institute of Technology Jodhpur,
Indian Institute of Information Technology Design and Manufacturing Jabalpur,
Indian Institute of Technology Delhi,
Malaviya National Institute of Technology Jaipur,
Indian Institute of Technology Kanpur
ORCID:
0000-0003-1440-0841
Observed ORCID:
0000-0003-1440-0841
OpenAlex ID:
A5021276636
PVT-Aware Design of Dopingless Dynamically Configurable Tunnel FET
2015
·
Avinash Lahgere
, Chitrakant Sahu
, et al.
·
IEEE Transactions on Electron Devices
·
90
Electrically doped dynamically configurable field‐effect transistor for low‐power and high‐performance applications
2015
·
A. Lahgere
, C. Sahu
, et al.
·
Electronics Letters
·
49
PDF
1-T Capacitorless DRAM Using Bandgap-Engineered Silicon-Germanium Bipolar I-MOS
2017
·
Avinash Lahgere
, Mamidala Jagadesh Kumar
·
IEEE Transactions on Electron Devices
·
41
Dopingless ferroelectric tunnel FET architecture for the improvement of performance of dopingless n-channel tunnel FETs
2016
·
Avinash Lahgere
, Meena Panchore
, et al.
·
Superlattices and Microstructures
·
37
The Charge Plasma n-p-n Impact Ionization MOS on FDSOI Technology: Proposal and Analysis
2016
·
Avinash Lahgere
, Mamidala Jagadesh Kumar
·
IEEE Transactions on Electron Devices
·
28
Evaluation of Radiation Resiliency on Emerging Junctionless/Dopingless Devices and Circuits
2019
·
Neha Kamal
, Avinash Lahgere
, et al.
·
IEEE Transactions on Device and Materials Reliability
·
21
1-T Capacitorless DRAM Using Laterally Bandgap Engineered Si-Si:C Heterostructure Bipolar I-MOS for Improved Sensing Margin and Retention Time
2018
·
Avinash Lahgere
, Mamidala Jagadesh Kumar
·
IEEE Transactions on Nanotechnology
·
18
A Tunnel Dielectric-Based Junctionless Transistor With Reduced Parasitic BJT Action
2017
·
Avinash Lahgere
, Mamidala Jagadesh Kumar
·
IEEE Transactions on Electron Devices
·
18
High-Performance Dielectric Modulated Epitaxial Tunnel Layer Tunnel FET for Label-Free Detection of Biomolecules
2024
·
Kunal Aggarwal
, Avinash Lahgere
·
IEEE Open Journal of Nanotechnology
·
15
Design of Leaky Integrate and Fire Neuron for Spiking Neural Networks Using Trench Bipolar I-MOS
2023
·
Avinash Lahgere
·
IEEE Transactions on Nanotechnology
·
13
Ultra-Low Power Reconfigurable Synaptic and Neuronal Transistor for Spiking Neural Network
2023
·
Neha Kamal
, Jawar Singh
, et al.
·
IEEE Transactions on Nanotechnology
·
10
Comprehensive analysis and investigation of GaN LNA for 3–4 GHz using different gate-drain spacing
2025
·
Md Hasnain Ansari
, Siddharth Thakur
, et al.
·
Microelectronic Engineering
·
9
Comprehensive TCAD-Based Single Event Effect Study of TFET-Based 1T DRAM and Crossbar Memory Array
2025
·
Dhananjay Prakash
, Neha Kamal
, et al.
·
IEEE Transactions on Device and Materials Reliability
·
9
An Investigation of Minimum Supply Voltage of 5-nm SRAM From 300 K Down to 10 K
2025
·
Hafeez Raza
, Shivendra Singh Parihar
, et al.
·
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
·
9
Band-to-Band Tunneling Based Unified RAM (URAM) for Low Power Embedded Applications
2024
·
Avinash Lahgere
, Alok Kumar Kamal
, et al.
·
IEEE Transactions on Nanotechnology
·
7
Physics-Based SPICE Model of Slant Field Plate GaN HEMTs
2025
·
Md Hasnain Ansari
, Avinash Lahgere
, et al.
·
IEEE Transactions on Electron Devices
·
4
Scalability Prespective of Nanotube TFET Capacitorless DRAM in Sub-20 nm Regime
2024
·
Alok Kumar Kamal
, Neha Kamal
, et al.
·
IEEE Latin American Electron Devices Conference (LAEDC)
·
4
A Dynamically Configurable Silicon Nanowire Field Effect Transistor based on Electrically Doped Source/Drain
2014
·
Sahu, Chitrakant
, Lahgere, Avinash
, et al.
·
arXiv (Cornell University)
·
4
PDF
A Comprehensive Analysis of Safe Operating Area Limits in Ferroelectric-Based DEMOS
2024
·
Garima Gill
, Anant Singhal
, et al.
·
IEEE Transactions on Electron Devices
·
3
Improved Compact Modeling of Snapback Behaviour in ESD MOSFETs
2024
·
Anant Singhal
, Garima Gill
, et al.
·
International Conference on Simulation of Semiconductor Processes and Devices
·
2
A Simulation Study of Bipolar I-MOS for ESD Protection
2023
·
Avinash Lahgere
, Dhruv Shikhar Gupta
·
IEEE Transactions on Electron Devices
·
2
Gate Grounded Trench I-MOS as an ESD Clamp for Sub-2V Applications
2023
·
Avinash Lahgere
, Dhruv Shikhar Gupta
·
IEEE Access
·
2
PDF
Evaluation of Radiation Resilience, Performance, and V min of Sub-3 nm FSFET Based SRAM Arrays
2025
·
Hafeez Raza
, Mahdi Benkhelifa
, et al.
·
IEEE Transactions on Computers
·
1
Energy Efficient Negative Capacitance L-Shaped Tunnel Field Effect Transistor
2025
·
Alok Kumar Kamal
, Neha Kamal
, et al.
·
IEEE Region 10 Conference (TENCON)
·
1
A Novel Dual-Band Matching Circuit Covering Wide Frequency Ratio suitable for 5G applications
2024
·
G Samykutha
, Shubham Sharma
, et al.
·
IEEE Microwaves, Antennas, and Propagation Conference (MAPCON)
·
1
Show more works
View as search
Works count:
41
Citation count:
399
H-index:
10
I10-index:
11
Year
Topic
Type
