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Titu Mary Ignatius
Institution:
Indian Institute of Technology Guwahati
Observed institution:
Indian Institute of Technology Guwahati
ORCID:
0000-0001-7794-653X
Observed ORCID:
0000-0001-7794-653X
OpenAlex ID:
A5021635693
Power Side-Channel Attacks on Crypto-Core Based on RISC-V ISA for High-Security Applications
2024
·
Titu Mary Ignatius
, Thockchom Birjit Singha
, et al.
·
IEEE Access
·
9
A Serial-Parallel-Based 4-Bit Novel Multiplier: Design, Implementation, and Performance Analysis
2023
·
Vishnu Padmakumar
, Titu Mary Ignatius
, et al.
·
IEEE Silchar Subsection Conference (SILCON)
·
6
Non-Linear Cyclic Variable Clock Feistel Bridge-Inspired Countermeasure for Securing RISC-V Crypto-Core Against Power Attacks
2025
·
Titu Mary Ignatius
, Roy Paily Palathinkal
·
IEEE Transactions on Circuits and Systems I Regular Papers
·
5
Impact of Pipelining on Low Power IoT applicable RISC-V ISA Core Micro-architectures
2024
·
Titu Mary Ignatius
, Satyajit Bora
, et al.
·
IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)
·
5
Implementation of high performance dynamic flash ADC
2014
·
Titu Mary Ignatius
, Jobin. K. Antony
, et al.
·
Annual International Conference on Emerging Research Areas and International Conference on Microelectronics, Communications and Renewable Energy
·
5
Boosting AES Intrinsic Resilience Using Split SubBytes Round Function Against Power Attacks
2024
·
Vishnu Padmakumar
, Titu Mary Ignatius
, et al.
·
IEEE Embedded Systems Letters
·
4
Improvement in Resilience of AES Design With Reconfigured CFB Mode Against Power Attacks
2024
·
Thockchom Birjit Singha
, Basa Sanjana
, et al.
·
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
·
3
RAESC: A Reconfigurable AES Countermeasure Architecture for RISC-V With Enhanced Power Side-Channel Resilience
2025
·
Nayana Rajeev
, Cathrene Biju
, et al.
·
IEEE Computer Architecture Letters
·
2
A High Speed 32-bit Approximate Adder with Improved Accuracy
2023
·
Jhumur Santra
, Anupam Kumari
, et al.
·
IEEE Silchar Subsection Conference (SILCON)
·
2
Securing RISC-V SoC With Random Clock Self Complementary Countermeasure
2025
·
Titu Mary Ignatius
, Roy Paily Palathinkal
·
IEEE Embedded Systems Letters
·
1
Low-Overhead Power Side-Channel Resistant AES Accelerator for RISC-V via Stall-Induced Trace Desynchronization and Activity Equalization
2026
·
Anupam Kumari
, Titu Mary Ignatius
, et al.
·
IEEE Transactions on Circuits & Systems II Express Briefs
Novel PRNG Design with Seed Updation Policy Using Fibonacci Sequence Generator
2025
·
Debarthy Deb
, Anupam Kumari
, et al.
·
Lecture notes in electrical engineering
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Works count:
12
Citation count:
42
H-index:
5
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