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Pinalkumar J. Engineer

Observed names: J. Pinalkumar, Pinal Engineer, Pinalkumar Engineer
ORCID: 0000-0002-4955-232X
Observed ORCID: 0000-0002-4955-232X
OpenAlex ID: A5021861495
Role of IOT in healthcare: Applications, security & privacy concerns
2024 · Akshay Parihar, Jigna B. Prajapati, et al. · Intelligent Pharmacy · 42
High-Speed Energy-Efficient Fixed-Point Signed Multipliers for FPGA-Based DSP Applications
2024 · Mitul Sudhirkumar Nagar, Aditya Mathuriya, et al. · IEEE Embedded Systems Letters · 25
Fabric surface defect classification and systematic analysis using a cuckoo search optimized deep residual network
2024 · Hiren Mewada, Ivan Miguel Pires, et al. · Engineering Science and Technology an International Journal · 24
Leave-One-Out Cross-Validation in Machine Learning
2023 · Radhika Sreedharan, Jigna Prajapati, et al. · CRC Press eBooks · 21
FPGA Implementation of Particle Filter Based Object Tracking in Video
2012 · Sumeet Agrawal, Pinal Engineer, et al. · International Symposium on Electronic System Design · 11
Memory-efficient Edge-based Non-Neural Face Recognition Algorithm on the Parallel Ultra-Low Power (PULP) Cluster
2023 · Mitul Sudhirkumar Nagar, Sayantan Maiti, et al. · IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC) · 6
Parallelizing Non-Neural ML Algorithm for Edge-based Face Recognition on Parallel Ultra-Low Power (PULP) Cluster
2023 · Mitul Sudhirkumar Nagar, Rahul Kumar, et al. · Mediterranean Conference on Embedded Computing (MECO) · 6
Parameterizable FPGA Framework for Particle Filter Based Object Tracking in Video
2015 · Pinalkumar Engineer, Rajbabu Velmurugan, et al. · International Conference on VLSI Design · 6
A Template-Based Methodology for Efficient DNNs Inference on FPGA Devices With HW-SW Co-Design
2025 · Swati, Shantanu Banarjee, et al. · IEEE Embedded Systems Letters · 5
FPGA-Based High-Speed Energy-Efficient 32-Bit Fixed-Point MAC Architecture for DSP Application in IoT Edge Computing
2024 · Mitul Sudhirkumar Nagar, Sohan H. Patel, et al. · Journal of Circuits Systems and Computers · 5
A Memory Efficient Run-time Re-configurable Convolution IP Core for Deep Neural Networks Inference on FPGA Devices
2023 · Swati, Ranajoy Sadhukhan, et al. · IEEE International Symposium on Smart Electronic Systems (iSES) · 5
Energy-Efficient Acceleration of Deep Learning based Facial Recognition on RISC-V Processor
2023 · Mitul Sudhirkumar Nagar, Vivek Chauhan, et al. · International Conference on Intelligent Systems and Embedded Design (ISED) · 5
Design and implementation of quasi cyclic low density parity check (QC-LDPC) code on FPGA
2017 · Dharmesh J. Patel, Pinalkumar Engineer · International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET) · 5
Modified architecture for real-time face detection using FPGA
2012 · Suraj Das, Atit Jariwala, et al. · Nirma University International Conference on Engineering · 5
Efficient Deep Learning based License Plate Recognition for Smart Cities
2024 · Swati Swati, Shubh Dinesh Kawa, et al. · ELCVIA Electronic Letters on Computer Vision and Image Analysis · 4
Quantization Effects on a Convolutional Layer of a Deep Neural Network
2023 · Swati, Dheeraj Verma, et al. · Smart innovation, systems and technologies · 4
Scalable implementation of particle filter-based visual object tracking on network-on-chip (NoC)
2019 · Pinalkumar Engineer, Rajbabu Velmurugan, et al. · Journal of Real-Time Image Processing · 4
Energy-efficient Non-Neural Face Recognition on the Multi-core RISC-V System
2025 · Mitul Sudhirkumar Nagar, Pinalkumar Engineer · IEEE International Symposium on Circuits and Systems proceedings · 3
A review on Beamspace Channel Estimation Algorithms in Wireless Communication
2023 · Smita G. Daware, Pinalkumar Engineer, et al. · IEEE Conference on Information and Communication Technology (CICT) · 3
Smart Farming Ingredients
2023 · Jigna Bhupendra Prajapati, Roshani Barad, et al. · Advances in environmental engineering and green technologies book series · 3
An Efficient Object Tracking on Edge Devices with Quantized Siamese Networks
2025 · Swati, Vasikarla Nikhil Kumar, et al. · Devices for Integrated Circuit (DevIC) · 2
Image Communication Using Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) Code
2020 · Dharmesh Jayantibhai Patel, Pinalkumar Engineer, et al. · Lecture notes in electrical engineering · 2
Parallelized Memory Oriented Manual Tiling-based Energy-Efficient Non-Neural Face Recognition Algorithm on GAP8
2026 · Mitul Sudhirkumar Nagar, Pinalkumar Engineer · Journal of Systems Architecture · 1
Edge AI Acceleration on Ultra96 SoC: Rapid Model-to-FPGA Hardware Mapping Using NNgen
2025 · Swati, Harshkumar Parmar, et al. · International Conference on Intelligent Systems and Embedded Design (ISED) · 1
Optimized Architecture of Energy-Intent Accelerator for the Non-Neural Face Recognition on the Edge
2025 · Mitul Sudhirkumar Nagar, Pinalkumar Engineer · IEEE International Symposium on Smart Electronic Systems (iSES) · 1
Works count: 39
Citation count: 202
H-index: 6
I10-index: 5
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