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C. Pakkiraiah

Observed name: Pakkiraiah C
Observed institution: Sri Venkateswara University
ORCID: 0000-0003-4826-1640
Observed ORCID: 0000-0003-4826-1640
OpenAlex ID: A5022810556
An Innovative Design of Low Power Binary Adder based on Switching Activity
2022 · C. Pakkiraiah, Dr. R.V.S. Satyanarayana · International Journal of Computing and Digital Systems · 10
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FPGA realization of low power multi-layer perceptron full adder to minimize EDP of modular multiplier
2021 · Pakkiraiah C, R V S. Satyanarayana · International Journal of Electronics Engineering and Applications · 2
Design of Low Power Modular (x mod p) Reduction Unit Based on Switching Activity for Data Security Applications
2022 · C. Pakkiraiah, R. V. S. Satyanarayana · Lecture notes in electrical engineering · 1
Design of Low Power Artificial Hybrid Adder using Neural Network Classifiers to Minimize Energy Delay Product for Arithmetic Application
2022 · C. Pakkiraiah, R.V.S. Satyanarayana · International Journal of Computer Applications · 1
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Design and FPGA Realization of an Energy Efficient Artificial Neural Modular Exponentiation Architecture
2022 · C. Pakkiraiah, R. V. S. Satyanarayana · Communications in computer and information science · 1
Works count: 5
Citation count: 15
H-index: 2
I10-index: 1
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