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Sithara Raveendran

Observed names: R. Sithara, Sithara R.
ORCID: 0000-0001-5805-232X
Observed ORCID: 0000-0001-5805-232X
OpenAlex ID: A5023374061
Approximate Multiplier Design Using Novel Dual-Stage 4:2 Compressors
2020 · Pranose J. Edavoor, Sithara Raveendran, et al. · IEEE Access · 144
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Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic
2021 · Sithara Raveendran, Pranose J. Edavoor, et al. · IEEE Access · 30
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An Approximate Low-Power Lifting Scheme Using Reversible Logic
2020 · Sithara Raveendran, Pranose J. Edavoor, et al. · IEEE Access · 19
Design and Analysis of Energy Efficient Reversible Logic based Full Adder
2019 · Jagadeesh Pujar, Sithara Raveendran, et al. · IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) · 14
Design and Implementation of Reversible Logic based RGB to Gray scale Color Space Converter
2018 · Sithara Raveendran, Pranose J. Edavoor, et al. · IEEE Region 10 Conference (TENCON) · 13
FPGA Implementation of Square and Cube Architecture Using Vedic Mathematics
2018 · Sampada Barve, Sithara Raveendran, et al. · IEEE International Symposium on Smart Electronic Systems (iSES) · 9
Characterization of a Novel Low Leakage Power and Area Efficient 7T SRAM Cell
2016 · A. Venkatareddy, R. Sithara, et al. · International Conference on VLSI Design · 9
Design and implementation of image kernels using reversible logic gates
2020 · Sithara Raveendran, Pranose Jose Edavoor, et al. · IET Image Processing · 5
Novel 4:2 Approximate Compressor Designs for Multimedia and Neural Network Applications
2020 · Pranose J. Edavoor, Sithara Raveendran, et al. · Journal of Circuits Systems and Computers · 5
Design and implementation of computationally efficient architecture of PID based motion controller for robotic land navigation system in FPGA
2017 · Priyanandini Das, Pranose J. Edavoor, et al. · IEEE Conference on Information and Communication Technology (CICT) · 4
On The Design Of Rationalised Bi-orthogonal Wavelet Using Reversible Logic
2022 · Sithara Raveendran, Pranose J. Edavoor, et al. · IEEE International Symposium on Circuits and Systems proceedings · 2
Reversible Logic Implementation of Image Denoising for Grayscale Images
2020 · Sithara Raveendran, Pranose J. Edavoor, et al. · IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) · 2
Implementation of adaptive image compression algorithm using varying bit-length daubechies wavelet coefficient with three-level encryption on Zynq 7000
2017 · Pranose J Edavoor, Sithara Raveendran, et al. · International Symposium on Embedded Computing and System Design (ISED) · 2
Verilog implementation of adaptive compression of RGB images at low bit rates
2015 · Arjun T V, Pranose J Edavoor, et al. · IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) · 2
Approximate Three-Operand Binary Adder for Error-Resilient Applications
2023 · Darshan Halliyavar, Siddharth R. K., et al. · IEEE International Symposium on Smart Electronic Systems (iSES) · 1
Design and implementation of PID controller based on orthogonal wavelet filter-banks in FPGA
2017 · Priyanandini Das, Pranose J Edavoor, et al. · International Symposium on Embedded Computing and System Design (ISED) · 1
RGB to Grayscale and RGB to XYZ using Reversible Logic Circuits
2025 · Sithara Raveendran, Nancy Angel G, et al. · International Conference on Research Methodologies in Knowledge Management, Artificial Intelligence and Telecommunication Engineering (RMKMATE)
FPGA realisation of PSNR and BPP driven Adaptive Compression and Encryption Algorithm for RGB Images
2016 · Pranose J. Edavoor, Sithara Raveendran, et al. · International Conference on Computing, Communication and Networking Technologies (ICCCNT)
Works count: 18
Citation count: 262
H-index: 7
I10-index: 5
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