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Sigang Ryu

ORCID: 0000-0001-5307-8117
Observed ORCID: 0000-0001-5307-8117
OpenAlex ID: A5024860679
13.1 A 940MHz-bandwidth 28.8µs-period 8.9GHz chirp frequency synthesizer PLL in 65nm CMOS for X-band FMCW radar applications
2016 · Hwanseok Yeo, Sigang Ryu, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 40
30.1 A 40nm VLIW Edge Accelerator with 5MB of 0.256pJ/b RRAM and a Localization Solver for Bristle Robot Surveillance
2024 · Samuel D. Spetalnick, Ashwin Sanjay Lele, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 21
A 9.2 GHz Digital Phase-Locked Loop With Peaking-Free Transfer Function
2014 · Sigang Ryu, Hwanseok Yeo, et al. · IEEE Journal of Solid-State Circuits · 16
A 1.3-mW, 1.6-GHz digital delay-locked loop with two-cycle locking time and dither-free tracking
2013 · Kyunghoon Kim, Seuk Son, et al. · Symposium on VLSI Circuits · 12
A Time-Based Pipelined ADC Using Integrate-and-Fire Multiplying-DAC
2021 · Sigang Ryu, Chan Young Park, et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 7
An Edge Accelerator With 5 MB of 0.256-pJ/bit Embedded RRAM and a Localization Solver for Bristle Robot Surveillance
2024 · Samuel D. Spetalnick, Ashwin Sanjay Lele, et al. · IEEE Journal of Solid-State Circuits · 6
A 2$\times$ Blind Oversampling FSE Receiver With Combined Adaptive Equalization and Infinite-Range Timing Recovery
2019 · Seuk Son, Sigang Ryu, et al. · IEEE Journal of Solid-State Circuits · 6
A 9.2-GHz digital phase-locked loop with peaking-free transfer function
2013 · Sigang Ryu, Hwanseok Yeo, et al. · Custom Integrated Circuits Conference · 6
An Accurate and Noise-Resilient Spread-Spectrum Clock Tracking Aid for Digitally-Controlled Clock and Data Recovery Loops
2018 · Sigang Ryu, Seuk Son, et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 5
A 2× Blind Oversampling FSE Receiver with Combined Adaptive Equalization and Infinite-Range Timing Recovery
2018 · Seuk Son, Hwanseok Yeo, et al. · IEEE Asian Solid-State Circuits Conference (A-SSCC) · 5
MDS-DOA: Fusing Model-Based and Data-Driven Approaches for Modular, Distributed, and Scalable Direction-of-Arrival Estimation
2024 · Adou Sangbone Assoa, Ashwin Bhat, et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 4
A model-first design and verification flow for analog-digital convergence systems: A high-speed receiver example in digital TVs
2012 · Jaeha Kim, Sigang Ryu, et al. · IEEE International Symposium on Circuits and Systems proceedings · 4
A 65-nm Delta-Sigma ADC-Based VDD-Variation-Tolerant Power-Side-Channel-Attack Sensor
2025 · Shota Konno, Zachary J. Ellis, et al. · IEEE Solid-State Circuits Letters · 3
A Scalable Platform for Single-Snapshot Direction Of Arrival (DOA) Estimation in Massive MIMO Systems
2023 · Adou Sangbone Assoa, Ashwin Bhat, et al. · ACM Great Lakes Symposium on VLSI (GLSVLSI) · 3
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A 65nm Delta-Sigma ADC Based VDD-Variation-Tolerant Power-Side-Channel-Attack Monitor with Detection Capability Down to 0.25Ω
2024 · Shota Konno, Zachary J. Ellis, et al. · IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 2
Fractionally-Spaced Equalizers as Clock and Data Recovery Loops
2024 · Sigang Ryu, Jaeha Kim, et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 2
A 28 nm 1.80Mb/mm 2 Digital/Analog Hybrid SRAM-CIM Macro using 2D-Weighted Capacitor Array for Complex Number MAC Operations
2025 · Shota Konno, Che-Kai Liu, et al. · IEEE Asian Solid-State Circuits Conference (A-SSCC) · 1
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A Modular, Distributed and Scalable DOA Estimator for MIMO Systems
2024 · Adou Sangbone Assoa, Ashwin Bhat, et al. · IEEE MTT-S International Microwave Symposium digest · 1
A 65nm 60mW Dual-Loop Adaptive Digital Beamformer with Optimized Sidelobe Cancellation and On-Chip DOA Estimation for mm-Wave Applications
2023 · Sigang Ryu, Adou Sangbone Assoa, et al. · IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 1
XEDGE-SIM: Fast NPU-Level Simulator Unifying RRAM-Based CIM and Firmware-Aware Digital Subsystems for Mixed-Signal Verification
2026 · Jeong-Hoon Min, Ashwin Bhat, et al. · International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design
Works count: 20
Citation count: 145
H-index: 6
I10-index: 4
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