Get started
Author

Elio Guidetti

Observed name: E. Guidetti
OpenAlex ID: A5025029445
14.1 A 2.9TOPS/W deep convolutional neural network SoC in FD-SOI 28nm for intelligent embedded systems
2017 · Giuseppe Desoli, Nitin Chawla, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 179
A 10 pJ/cycle ultra-low-voltage 32-bit microprocessor system-on-chip
2011 · Nathan Ickes, Yildiz Sinangil, et al. · European Solid-State Circuits Conference (ESSCIRC) · 41
Implementing a 1GHz Four-Issue Out-of-Order Execution Microprocessor in a Standard Cell ASIC Methodology
2007 · Wei-Wu Hu, Ji-Ye Zhao, et al. · Journal of Computer Science and Technology · 21
An Integrated Low-power 802.11ba Wake-up Radio for IoT with Embedded Microprocessor
2022 · Marco Ronchi, Francesco Malena, et al. · IEEE International Conference on Electronics, Circuits and Systems (ICECS) · 3
The Orlando Project: A 28 nm FD-SOI Low Memory Embedded Neural Network ASIC
2016 · Giuseppe Desoli, Valeria Tomaselli, et al. · Lecture notes in computer science · 3
Fast and Accurate Modeling of RF Front-Ends for Wake-Up Radios: Implementation and Integration of Behavioral Blocks for System-Level Simulation
2025 · Vittoria Paoli, Ettore Noccetti, et al. · IEEE International Conference on Electronics, Circuits and Systems (ICECS) · 2
A Low-Cost Fault Tolerance Technique for Microcontroller-Class RISC-V Processors
2025 · Riccardo Tedeschi, Alessandro Nadalini, et al. · Lecture notes in electrical engineering · 2
A VLIW architecture for Prolog
1991 · Alessandro De Gloria, Paolo Faraboschi, et al. · 2
Design-Space Exploration of Integrated Frequency Synthesis Architecture for Wake-Up Radio in Low-Power Wi-Fi Applications
2025 · V. Paoli, M. Mestice, et al. · Lecture notes in electrical engineering · 1
ASIC and board design of a high performance parallel architecture
2003 · A. De Gloria, P. Faraboschi, et al. · Euro ASIC Conference (EURO ASIC) · 1
A Parallel Incremental Architecture for Prolog Program Execution
1991 · Alessandro De Gloria, Paolo Faraboschi, et al. · Springer eBooks · 1
A Fine-Grained Multithreaded RISC-V Core for Efficient and Predictable Real-Time Microcontrollers
2026 · Arbi Gunbardhi, Riccardo Tedeschi, et al. · Euromicro Conference on Digital System Design (DSD)
Temporal Lockstep: Low-Cost Resilient Design for Microcontroller-Class RISC-V Processors
2026 · Riccardo Tedeschi, Alessandro Nadalini, et al. · IEEE Access
インテリジェント埋込みシステムのためのFD‐SOI28nmにおける14.1‐2.9TOPS/W深い畳込みニューラルネットワークSoC【Powered by NICT】
2017 · Giuseppe Desoli, Nitin Chawla, et al. · IEEE Conference Proceedings
A 14-bit extended-range incremental ΣΔ ADC matlab-model based on 90nm CMOS-technology
2013 · D. Cavallo, M. De Matteis, et al. · IEEE International Conference on IC Design and Technology (ICICDT)
An Ultra-Low Power Data Aggregation System for Wireless Micro Sensor Networks
2007 · Giuseppe Visalli, Elio Guidetti · Journal of Low Power Electronics
A Low Power, Scalable and Runtime Customizable Microprocessor Architecture for Image Processing
2007 · Giuseppe Notarangelo, Francesco Pappalardo, et al. · Journal of Low Power Electronics
Knowledge-based multisensor data integration applied to road detection
2003 · P. Faraboschi, D.D. Giusto, et al. · Electrotechnical Conference Integrating Research, Industry and Education in Energy and Communication Engineering
Works count: 18
Citation count: 256
H-index: 3
I10-index: 3
Year
Topic
Type