Author

Jen‐Chieh Liu

Observed names: Jen-Chieh LIU, Jen-Chieh Liu

Institutions: National United University, Himax (Taiwan)

Observed institutions: Fu Jen Catholic University, National United University, National Yang Ming Chiao Tung University, Purdue University West Lafayette, National Central University, Industrial Technology Research Institute, Chung Hua University, Himax (Taiwan), Stanford University, National Taipei University

ORCID: 0000-0002-7045-6586

Observed ORCID: 0000-0002-7045-6586

OpenAlex ID: A5025566121

Stable Low-Voltage Operation Top-Gate Organic Field-Effect Transistors on Cellulose Nanocrystal Substrates

2015 · Cheng-Yin Wang, Canek Fuentes-Hernandez, et al. · ACS Applied Materials & Interfaces · 68

Statistical Model and Rapid Prediction of RRAM SET Speed–Disturb Dilemma

2013 · Wun-Cheng Luo, Jen-Chieh Liu, et al. · IEEE Transactions on Electron Devices · 46

Challenges and opportunities toward online training acceleration using RRAM-based hardware neural network

2017 · Chih-Cheng Chang, Jen-Chieh Liu, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 36

Built-in Jitter Measurement Circuit With Calibration Techniques for a 3-GHz Clock Generator

2010 · Kuo-Hsing Cheng, Jen-Chieh Liu, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 28

RRAM SET speed-disturb dilemma and rapid statistical prediction methodology

2012 · Wun-Cheng Luo, Jen-Chieh Liu, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 26

A 0.9- to 8-GHz VCO With a Differential Active Inductor for Multistandard Wireline SerDes

2014 · Kuo-Hsing Cheng, Cheng-Liang Hung, et al. · IEEE Transactions on Circuits & Systems II Express Briefs · 24

A 0.6-V 800-MHz All-Digital Phase-Locked Loop With a Digital Supply Regulator

2012 · Kuo-Hsing Cheng, Jen-Chieh Liu, et al. · IEEE Transactions on Circuits & Systems II Express Briefs · 24

High-gain and high-bandwidth rail-to-rail operational amplifier with slew rate boost circuit

2006 · Hong-Yi Huang, Bo-Ruei Wang, et al. · IEEE International Symposium on Circuits and Systems proceedings · 24

A High Precision Fast Locking Arbitrary Duty Cycle Clock Synchronization Circuit

2010 · Kuo-Hsing Cheng, Kai-Wei Hong, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 20

Optimizing Incremental Step Pulse Programming for RRAM Through Device–Circuit Co-Design

2018 · Jen-Chieh Liu, Tzu-Yun Wu, et al. · IEEE Transactions on Circuits & Systems II Express Briefs · 19

A High-Accuracy Programmable Pulse Generator With a 10-ps Timing Resolution

2018 · Jen-Chieh Liu, Chao-Jen Huang, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 18

A 6-GHz Built-in Jitter Measurement Circuit Using Multiphase Sampler

2011 · Kuo-Hsing Cheng, Jen-Chieh Liu, et al. · IEEE Transactions on Circuits & Systems II Express Briefs · 13

A Power-Saving Adaptive Equalizer With a Digital-Controlled Self-Slope Detection

2018 · Yo-Hao Tu, Kuo-Hsing Cheng, et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 11

A Low Supply Voltage All-Digital Phase-Locked Loop With a Bootstrapped and Forward Interpolation Digitally Controlled Oscillator

2021 · Jen-Chieh Liu, Yu-Ping Li · IEEE Access · 9

A 0.3-V all digital crystal-less clock generator for energy harvester applications

2012 · Jen-Chieh Liu, Wei Chun Lee, et al. · IEEE Asian Solid-State Circuits Conference (A-SSCC) · 9

A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop

2010 · Kuo-Hsing Cheng, Chang-Chien Hu, et al. · IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) · 9

Neuromorphic pattern learning using HBM electronic synapse with excitatory and inhibitory plasticity

2015 · Teyuh Chou, Jen-Chieh Liu, et al. · International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) · 8

Optimization of Source Modeling From Phaseless Near-Field Scanning Based on SVD-Defined Eigenmodes

2024 · Min-Hsu Tsai, Hong-Wen Qian, et al. · IEEE Transactions on Electromagnetic Compatibility · 7

A low-jitter all-digital PLL with high-linearity DCO

2018 · Yu-Lung Lo, Hsi-Hua Wang, et al. · Microsystem Technologies · 6

A 0.6-V 1.6-GHz 8-phase all digital PLL using multi-phase based TDC

2015 · Yo-Hao Tu, Jen-Chieh Liu, et al. · IEICE Electronics Express · 6

PDF

All-Digital PLL Using Pulse-Based DCO

2007 · Hong-Yi Huang, Jen-Chieh Liu, et al. · IEEE International Conference on Electronics, Circuits and Systems (ICECS) · 6

A Low Power Pulse Generator for Test Platform Applications

2016 · Jen-Chieh LIU, Pei-Ying LEE · IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences · 5

A Low-power PLL with a Standby Mode

2024 · Yu-Chun Hsiao, Rui-Cheng Ai, et al. · International SoC Design Conference · 4

Low supply voltage and multiphase all‐digital crystal‐less clock generator

2018 · Yo‐Hao Tu, Jen‐Chieh Liu, et al. · IET Circuits Devices & Systems · 4

PVT Insensitive High-Resolution Time to Digital Converter for Intraocular Pressure Sensing

2015 · Hong-Yi Huang, Jen-Chieh Liu, et al. · IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) · 4

Works count: 59

Citation count: 472

H-index: 12

I10-index: 13