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Pascal Meinerzhagen

Observed names: Meinerzhagen Pascal, Meinerzhagen, Pascal, Meinerzhagen, Pascal Andreas, P Meinerzhagen, P. Meinerzhagen, Pascal A. Meinerzhagen, Pascal Andreas Meinerzhagen
ORCID: 0000-0002-5444-5772
Observed ORCID: 0000-0002-5444-5772
OpenAlex ID: A5026324911
A successive cancellation decoder ASIC for a 1024-bit polar code in 180nm CMOS
2012 · A. Mishra, A. J. Raymond, et al. · IEEE Asian Solid-State Circuits Conference (A-SSCC) · 84
Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design
2014 · Ibrahim Kazi, Pascal Meinerzhagen, et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 76
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Benchmarking of Standard-Cell Based Memories in the Sub-$V_{\rm T}$ Domain in 65-nm CMOS Technology
2011 · Pascal Meinerzhagen, S. M. Yasser Sherazi, et al. · IEEE Journal on Emerging and Selected Topics in Circuits and Systems · 68
Towards generic low-power area-efficient standard cell based memory architectures
2010 · P. Meinerzhagen, C. Roth, et al. · Conference proceedings · 65
Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement
2016 · Adam Teman, Davide Rossi, et al. · ACM Transactions on Design Automation of Electronic Systems · 59
A Low-Voltage Radiation-Hardened 13T SRAM Bitcell for Ultralow Power Space Applications
2016 · Lior Atias, Adam Teman, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 56
Exploration of Sub-VT and Near-VT 2T Gain-Cell Memories for Ultra-Low Power Applications under Technology Scaling
2013 · Pascal Meinerzhagen, Adam Teman, et al. · Journal of Low Power Electronics and Applications · 46
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Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip
2017 · Pascal Meinerzhagen, Adam Teman, et al. · Springer eBooks · 44
Review and classification of gain cell eDRAM implementations
2012 · Adam Teman, Pascal Meinerzhagen, et al. · IEEE Convention of Electrical and Electronics Engineers in Israel · 43
Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications
2015 · Robert Giterman, Adam Teman, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 40
A 15.8 pJ/bit/iter quasi-cyclic LDPC decoder for IEEE 802.11n in 90 nm CMOS
2010 · C Roth, P Meinerzhagen, et al. · IEEE Asian Solid-State Circuits Conference (A-SSCC) · 35
Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM
2014 · Adam Teman, Pascal Meinerzhagen, et al. · IEEE Transactions on Circuits & Systems II Express Briefs · 32
A ReRAM-based non-volatile flip-flop with sub-VT read and CMOS voltage-compatible write
2013 · Ibrahim Kazi, Pascal Meinerzhagen, et al. · IEEE International New Circuits and Systems Conference (NEWCAS) · 31
TamaRISC-CS: An ultra-low-power application-specific processor for compressed sensing
2012 · Jeremy Constantin, Ahmed Dogan, et al. · IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC) · 31
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An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS
2018 · Pascal Meinerzhagen, Carlos Tokunaga, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 30
A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS
2012 · Pascal Meinerzhagen, Oskar Andersson, et al. · 29
Controlled placement of standard cell memory arrays for high density and low power in 28nm FD-SOI
2015 · Adam Teman, Davide Rossi, et al. · 28
4T Gain-Cell with internal-feedback for ultra-low retention power at scaled CMOS nodes
2014 · Robert Giterman, Adam Teman, et al. · IEEE International Symposium on Circuits and Systems proceedings · 28
An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{\text{MIN}}$ Optimization
2018 · Pascal A. Meinerzhagen, Carlos Tokunaga, et al. · IEEE Journal of Solid-State Circuits · 23
Energy versus Data Integrity Trade-Offs in Embedded High-Density Logic Compatible Dynamic Memories
2015 · Adam Teman, Georgios Karakonstantis, et al. · Design, Automation, and Test in Europe · 23
Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS
2016 · Oskar Andersson, Babak Mohammadi, et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 22
Silicon-Proven, Per-Cell Retention Time Distribution Model for Gain-Cell Based eDRAMs
2016 · Noa Edri, Pascal Meinerzhagen, et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 22
Impact of body biasing on the retention time of gain‐cell memories
2013 · Pascal Meinerzhagen, Adam Teman, et al. · The Journal of Engineering · 22
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A sub-VT 2T gain-cell memory for biomedical applications
2012 · Pascal Meinerzhagen, Adam Teman, et al. · 16
Analysis of Neutron-Induced Multibit-Upset Clusters in a 14-nm Flip-Flop Array
2019 · Saurabh Kumar, Minki Cho, et al. · IEEE Transactions on Nuclear Science · 14
Works count: 80
Citation count: 1,146
H-index: 22
I10-index: 33
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