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Adam Teman
Observed names:
A. Teman,
Teman A.,
Teman, Adam
Institutions:
Bar-Ilan University,
Indian Institute of Technology Indore
Observed institutions:
Ben-Gurion University of the Negev,
Bar-Ilan University,
University of Calgary,
École Polytechnique Fédérale de Lausanne,
Indian Institute of Technology Indore
ORCID:
0000-0002-8233-4711
Observed ORCID:
0000-0002-8233-4711
OpenAlex ID:
A5026444183
A 250 mV 8 kb 40 nm Ultra-Low Power 9T Supply Feedback SRAM (SF-SRAM)
2011
·
Adam Teman
, Lidor Pergament
, et al.
·
IEEE Journal of Solid-State Circuits
·
115
A 588-Gb/s LDPC Decoder Based on Finite-Alphabet Message Passing
2017
·
Reza Ghanaatian
, Alexios Balatsoukas-Stimming
, et al.
·
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
·
84
PDF
Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster
2017
·
Davide Rossi
, Antonio Pullini
, et al.
·
IEEE Micro
·
62
Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement
2016
·
Adam Teman
, Davide Rossi
, et al.
·
ACM Transactions on Design Automation of Electronic Systems
·
59
A Low-Voltage Radiation-Hardened 13T SRAM Bitcell for Ultralow Power Space Applications
2016
·
Lior Atias
, Adam Teman
, et al.
·
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
·
56
AM4: MRAM Crossbar Based CAM/TCAM/ACAM/AP for In-Memory Computing
2023
·
Esteban Garzón
, Marco Lanuzza
, et al.
·
IEEE Journal on Emerging and Selected Topics in Circuits and Systems
·
55
PDF
Hamming Distance Tolerant Content-Addressable Memory (HD-CAM) for DNA Classification
2022
·
Esteban Garzon
, Roman Golman
, et al.
·
IEEE Access
·
54
PDF
A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI
2017
·
Robert Giterman
, Alexander Fish
, et al.
·
IEEE Transactions on Circuits and Systems I Regular Papers
·
53
An 800-MHz Mixed- $V_{\text{T}}$ 4T IFGC Embedded DRAM in 28-nm CMOS Bulk Process for Approximate Storage Applications
2018
·
Robert Giterman
, Alexander Fish
, et al.
·
IEEE Journal of Solid-State Circuits
·
50
Exploration of Sub-VT and Near-VT 2T Gain-Cell Memories for Ultra-Low Power Applications under Technology Scaling
2013
·
Pascal Meinerzhagen
, Adam Teman
, et al.
·
Journal of Low Power Electronics and Applications
·
46
PDF
Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip
2017
·
Pascal Meinerzhagen
, Adam Teman
, et al.
·
Springer eBooks
·
44
Review and classification of gain cell eDRAM implementations
2012
·
Adam Teman
, Pascal Meinerzhagen
, et al.
·
IEEE Convention of Electrical and Electronics Engineers in Israel
·
43
Digital subthreshold logic design - motivation and challenges
2008
·
Sagi Fisher
, Adam Teman
, et al.
·
IEEE Convention of Electrical and Electronics Engineers in Israel
·
43
Gain-Cell Embedded DRAM Under Cryogenic Operation—A First Study
2021
·
Esteban Garzon
, Yosi Greenblatt
, et al.
·
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
·
41
Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications
2015
·
Robert Giterman
, Adam Teman
, et al.
·
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
·
40
EDAM
2022
·
Robert Hanhan
, Esteban Garzón
, et al.
·
Proceedings - International Symposium on Computer Architecture/Proceedings
·
37
Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications
2016
·
Robert Giterman
, Lior Atias
, et al.
·
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
·
36
A 40-nm Sub-Threshold 5T SRAM Bit Cell With Improved Read and Write Stability
2012
·
Adam Teman
, Anatoli Mordakhay
, et al.
·
IEEE Transactions on Circuits & Systems II Express Briefs
·
34
Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM
2014
·
Adam Teman
, Pascal Meinerzhagen
, et al.
·
IEEE Transactions on Circuits & Systems II Express Briefs
·
32
Exploiting STT-MRAMs for Cryogenic Non-Volatile Cache Applications
2021
·
Esteban Garzon
, Raffaele De Rose
, et al.
·
IEEE Transactions on Nanotechnology
·
31
An overlap-contention free true-single-phase clock dual-edge-triggered flip-flop
2015
·
Andrea Bonetti
, Adam Teman
, et al.
·
IEEE International Symposium on Circuits and Systems proceedings
·
31
Mitigating the impact of faults in unreliable memories for error-resilient applications
2015
·
Shrikanth Ganapathy
, Georgios Karakonstantis
, et al.
·
Proceedings - ACM IEEE Design Automation Conference
·
30
PDF
A Low-Power Low-Cost 24 GHz RFID Tag With a C-Flash Based Embedded Memory
2014
·
Hadar Dagan
, Aviv Shapira
, et al.
·
IEEE Journal of Solid-State Circuits
·
30
A 1-Mbit Fully Logic-Compatible 3T Gain-Cell Embedded DRAM in 16-nm FinFET
2020
·
Robert Giterman
, Amir Shalom
, et al.
·
IEEE Solid-State Circuits Letters
·
29
193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing
2016
·
Davide Rossi
, Antonio Pullini
, et al.
·
IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)
·
28
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Works count:
170
Citation count:
2,043
H-index:
27
I10-index:
62
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