Author

Basavoju Harish

Observed name: B. Harish

Institution: Vignan's Foundation for Science, Technology & Research

Observed institution: Vignan's Foundation for Science, Technology & Research

ORCID: 0000-0001-9336-2155

Observed ORCID: 0000-0001-9336-2155

OpenAlex ID: A5026467902

Design and Performance Comparison among Various types of Adder Topologies

2019 · Basavoju Harish, K. Sivani, et al. · International Conference on Computing Methodologies and Communication (ICCMC) · 27

Performance comparison of various CMOS full adders

2017 · Basavoju Harish, K. Sivani, et al. · International Conference on Energy, Communication, Data Analytics and Soft Computing (ICECDS) · 9

A novel air writing recognition system using Raspberry Pi for the control and interaction of digital systems

2017 · D. Udaya Lakshmi, B. Harish · International Conference on Energy, Communication, Data Analytics and Soft Computing (ICECDS) · 8

Implementation of High Speed 64-Bit Dadda Multiplier By Using 4:2 Compressor and Brent-Kung Adder

2025 · Basavoju Harish, Pusuluri Pavansai, et al. · IEEE International Conference on Information Technology, Electronics and Intelligent Communication Systems (ICITEICS) · 1

Ultra high speed full adder for biomedical applications

2021 · Basavoju Harish, M. S. S. Rukmini · International Journal of Reconfigurable and Embedded Systems (IJRES) · 1

PDF

64‐Bit High Speed Parallel Prefix Adder Architectures

2025 · B. Harish, M.S.S. Rukmini · Wiley eBooks

Design and Implementation of High‐Performance Adaptive Baud Rate Generator for IoT Applications

2025 · B. Harish, N. Jahnavi, et al. · Wiley eBooks

Design and Implementation of 64-Bit MAC Unit Using High Speed 64-Bit Vedic Multiplier and Brent-Kung Adder Architecture

2025 · Basavoju Harish, Miriyala Srividya, et al.

Enhancement of ON-Current in Modified TMG Vertical TFET with Split Pockets

2024 · K. Sivani, B. Harish, et al. · Research Square

PDF

High Performance Fir Filter Based on Pipelined Parallel Prefix Adder for Signal Processing Applications

2022 · Basavoju Harish, Rukmini M.S.S., et al. · ICTACT Journal on Microelectronics

Comparison of Multiplexer based Pseudo-Carry Compensation Truncated Multiplier with Standard Multipliers

2015 · M P Sunil, Kalvala Abhilash, et al. · IJSRD : international journal for scientific research and development

FPGA implementation of multiplierless 5/3 LeGall discrete wavelet transform using lifting approach

2011 · A. Naregalkar, B. Harish, et al. · International Conference & Workshop on Emerging Trends in Technology

Works count: 13

Citation count: 46

H-index: 3

I10-index: 1