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Fujun Bai

Observed name: Bai Fujun
ORCID: 0000-0002-7971-5986
Observed ORCID: 0000-0002-7971-5986
OpenAlex ID: A5026808971
A Stacked Embedded DRAM Array for LPDDR4/4X using Hybrid Bonding 3D Integration with 34GB/s/1Gb 0.88pJ/b Logic-to-Memory Interface
2020 · Bai Fujun, Jiang Xiping, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 44
A 135 GBps/Gbit 0.66 pJ/bit Stacked Embedded DRAM with Multilayer Arrays by Fine Pitch Hybrid Bonding and Mini-TSV
2023 · Song Wang, Bing Yu, et al. · IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 31
Semantic Segmentation of Panoramic Images for Real-Time Parking Slot Detection
2022 · Cong Lai, Qingyu Yang, et al. · Remote Sensing · 19
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A True Process-Heterogeneous Stacked Embedded DRAM Structure Based on Wafer-Level Hybrid Bonding
2023 · Song Wang, Xiping Jiang, et al. · Electronics · 13
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A Low-Cost Reduced-Latency DRAM Architecture With Dynamic Reconfiguration of Row Decoder
2022 · Fujun Bai, Song Wang, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 13
A Watermarking Technique for Hard IP Protection in Full-custom IC Design
2007 · Fujun Bai, Zhiqiang Gao, et al. · International Conference on Communications, Circuits and Systems · 11
Hf0.5Zr0.5O2 1T−1C FeRAM arrays with excellent endurance performance for embedded memory
2023 · Wenwu Xiao, Yue Peng, et al. · Science China Information Sciences · 7
A watermarking technique for hard IP protection in post-layout design level
2007 · Xueyu Cai, Zhiqiang Gao, et al. · IEEE International Conference on ASIC (ASICON) · 7
A two-port SRAM using a single-port cell array with a self-timed write-after-read control scheme to save 47% area & 63% standby power
2017 · Fujun Bai, Baoyu Xiong, et al. · IEEE International Conference on ASIC (ASICON) · 6
A 1.2GHz 12.77GB/s/mm 2 3D Two-DRAM-One-Logic Process-Near-Memory Chip for Edge LLM Applications
2026 · Yue Cao, Jinghao Jiang, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 2
SSA-over-array (SSoA): A stacked DRAM architecture for near-memory computing
2024 · Xiping Jiang, Fujun Bai, et al. · Journal of Semiconductors · 2
A 3D Unified Analysis Method (3D-UAM) for Wafer-on-Wafer Stacked Near-Memory Structure
2025 · Song Wang, Yixin Guo, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 1
Design of watermarking systems for IP protection
2008 · Yangshuo Ding, Yun Du, et al. · IEEE International Conference on Solid-State and Integrated Circuit Technology · 1
A Comprehensive Analysis and Chip Implementation of Hybrid-Bonding-Based 3D-DRAM Process-Near-Memory Design for LLM Inference
2026 · Yue Cao, Jinghao Jiang, et al. · IEEE Journal of Solid-State Circuits
Works count: 16
Citation count: 160
H-index: 7
I10-index: 6
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