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D. Doyle

Observed names: D.J. Doyle, D.J.F. Doyle, Denis Doyle, Denis J. Doyle
OpenAlex ID: A5027085724
Statistical modeling for a 0.6 μm BiCMOS technology
2002 · J.A. Power, S.C. Kelly, et al. · IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM) · 9
Investigation of High-Voltage MOSFET Reliability in $I_{\rm KIRK}$ Region
2007 · Vicky O'Donovan, Anne Deignan, et al. · IEEE Transactions on Device and Materials Reliability · 6
The Impact of Rapid Thermal Annealing on the Properties of the Si (100)-SiO2 Interface
1998 · P.K. Hurley, C. Leveugle, et al. · MRS Proceedings · 6
Comparison of bipolar NPN polysilicon emitter interface formation at three different manufacturing sites
1992 · D.J. Doyle, J.D. Barrett, et al. · IEEE Transactions on Semiconductor Manufacturing · 5
Circuit modeling of bipolar transistors for BiCMOS
1989 · D.J.F. Doyle, W.A. Lane · IEEE Journal of Solid-State Circuits · 4
The CAP-FET, a scaleable MEMS sensor technology on CMOS with programmable floating gate
2002 · E. Hynes, P. Elebert, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 2
0.6 μm BiCMOS technology for RF and high speed converter applications
2002 · D. Doyle, K. Moloney, et al. · IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM) · 1
EP120: A 0.35um, 3V/5V, Mixed-Signal/RF BiCMOS Technology
2000 · D. Doyle, K. Moloney, et al. · European Solid-State Device Research Conference · 1
Process characterisation of hot-carrier-induced β degradation in bipolar transistors for BiCMOS
1999 · A. Arshak, D. McDonagh, et al. · Microelectronics Reliability · 1
ABCMOS3: A High Precision, High Speed, Modular BiCMOS Process for Analog/Digital Applications
1993 · D. Doyle, M. O'Neill, et al. · European Solid-State Device Research Conference · 1
On the temperature dependence of polysilicon emitter transistors
1991 · Denis J. Doyle, William A. Lane · Microelectronic Engineering · 1
Self-consistent Modelling of npn and pnp Transistors
1989 · Ann Kellelher, D. Doyle, et al. · European Solid-State Device Research Conference · 1
Scaling of bipolar transistor analog properties for mixed analog/digital BiCMOS
2003 · D.J.F. Doyle, W.A. Lane · IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)
Dose Loss and Defect Mechanisms in Antimony Buried Layers for a 0.35um BiCMOS Process
2000 · A. Deignan, D. McAuliffe, et al. · European Solid-State Device Research Conference
Anomalous Stress Effects of Trench Isolation
1994 · D. Rohan, D. Doyle, et al. · European Solid-State Device Research Conference
A Simplified, Multi-Application Method for Process Design and its use in the Design of a lpm, Mixed-Signal BiCMOS Process
1993 · D. Doyle, W. A. Lanes
Improved bipolar transistor performance in CMOS by novel use of parasitic collector resistance
1990 · D.J.F. Doyle, W.A. Lane · IEEE Journal of Solid-State Circuits
A Bipolar DC Model for Transistors Fabricated in a CMOS Process
1987 · D. Doyle, W.A. Lane · European Solid-State Device Research Conference
Works count: 18
Citation count: 38
H-index: 4
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