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Gopal Raut

Observed name: Raut, Gopal
ORCID: 0000-0002-1046-9457
Observed ORCID: 0000-0002-1046-9457
OpenAlex ID: A5028707436
RECON: Resource-Efficient CORDIC-Based Neuron Architecture
2021 · Gopal Raut, Shubham Rai, et al. · IEEE Open Journal of Circuits and Systems · 47
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An Empirical Evaluation of Enhanced Performance Softmax Function in Deep Learning
2023 · Sumiran Mehra, Gopal Raut, et al. · IEEE Access · 42
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Flex-PE: Flexible and SIMD Multiprecision Processing Element for AI Workloads
2025 · Mukul Lokhande, Gopal Raut, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 40
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An accurate and noninvasive skin cancer screening based on imaging technique
2021 · Gunjan Rajput, Shashank Agrawal, et al. · International Journal of Imaging Systems and Technology · 40
In-Memory Computing with 6T SRAM for Multi-operator Logic Design
2023 · Narendra Singh Dhakad, Eshika Chittora, et al. · Circuits Systems and Signal Processing · 38
A CORDIC Based Configurable Activation Function for ANN Applications
2020 · Gopal Raut, Shubham Rai, et al. · IEEE Computer Society Annual Symposium on VLSI · 38
VLSI implementation of transcendental function hyperbolic tangent for deep neural network accelerators
2021 · Gunjan Rajput, Gopal Raut, et al. · Microprocessors and Microsystems · 29
Data multiplexed and hardware reused architecture for deep neural network accelerator
2021 · Gopal Raut, Anton Biasizzo, et al. · Neurocomputing · 28
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An Empirical Approach to Enhance Performance for Scalable CORDIC-Based Deep Neural Networks
2023 · Gopal Raut, Saurabh Karkun, et al. · ACM Transactions on Reconfigurable Technology and Systems · 26
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QuantMAC: Enhancing Hardware Performance in DNNs With Quantize Enabled Multiply-Accumulate Unit
2024 · Neha Ashar, Gopal Raut, et al. · IEEE Access · 25
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BitMAC: Bit-Serial Computation-Based Efficient Multiply-Accumulate Unit for DNN Accelerator
2022 · Harsh Chhajed, Gopal Raut, et al. · Circuits Systems and Signal Processing · 23
Retrospective: A CORDIC Based Configurable Activation Function for NN Applications
2025 · Omkar Kokane, Gopal Raut, et al. · IEEE Computer Society Annual Symposium on VLSI · 14
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LPRE: Logarithmic Posit-enabled Reconfigurable edge-AI Engine
2025 · Omkar Kokane, Mukul Lokhande, et al. · IEEE International Symposium on Circuits and Systems proceedings · 12
Hybrid ADDer: A Viable Solution for Efficient Design of MAC in DNNs
2023 · Vasundhara Trivedi, Khushbu Lalwani, et al. · Circuits Systems and Signal Processing · 12
Designing a Performance-Centric MAC Unit with Pipelined Architecture for DNN Accelerators
2023 · Gopal Raut, Jogesh Mukala, et al. · Circuits Systems and Signal Processing · 12
Soft error hardened voltage bootstrapped Schmitt trigger design for reliable circuits
2021 · Neha Gupta, Ambika Prasad Shah, et al. · Microelectronics Reliability · 12
A 2.4-GS/s Power-Efficient, High-Resolution Reconfigurable Dynamic Comparator for ADC Architecture
2020 · Gopal Raut, Ambika Prasad Shah, et al. · Circuits Systems and Signal Processing · 11
Efficient Low-Precision CORDIC Algorithm for Hardware Implementation of Artificial Neural Network
2019 · Gopal Raut, Vishal Bhartiy, et al. · Communications in computer and information science · 11
A SIMD Dynamic Fixed Point Processing Engine for DNN Accelerators
2024 · Gopal Raut, Pranose J Edavoor, et al. · International Symposium on Quality Electronic Design (ISQED) · 8
Design and Analysis of Posit Quire Processing Engine for Neural Network Applications
2023 · Pranose J Edavoor, Aneesh Raveendran, et al. · International Conference on VLSI Design · 8
A Precision-Aware Neuron Engine for DNN Accelerators
2024 · Sudheer Vishwakarma, Gopal Raut, et al. · SN Computer Science · 6
A Data Flow Scheduler for Multi-precision SIMD Processing Engine Systolic Array CNN Accelerators
2024 · Ritambhara Thakur, Pranose J Edavoor, et al. · IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT) · 5
Multi-Precision SIMD Posit Systolic Array Accelerator for Deep Learning
2025 · Gopal Raut, David Selvakumar, et al. · IEEE International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA) · 3
A Configurable Activation Function for Variable Bit-Precision DNN Hardware Accelerators
2023 · Sudheer Vishwakarma, Gopal Raut, et al. · IFIP advances in information and communication technology · 3
ASIC Implementation Of Biologically Inspired Spiking Neural Network
2019 · Gunjan Rajput, Gopal Raut, et al. · International Conference on Emerging Trends in Engineering and Technology (ICETET) · 3
Works count: 45
Citation count: 513
H-index: 12
I10-index: 18
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