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Yo‐Hao Tu
Observed names:
Yo-Hao TU,
Yo-Hao Tu
Institutions:
National Central University,
MediaTek (Taiwan)
Observed institutions:
National Central University,
MediaTek (Taiwan)
OpenAlex ID:
A5029344336
A Wide-Range All-Digital Delay-Locked Loop for DDR1–DDR5 Applications
2021
·
Chih-Wei Tsai
, Yu-Ting Chiu
, et al.
·
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
·
18
A low jitter delay-locked-loop applied for DDR4
2013
·
Yo-Hao Tu
, Kuo-Hsing Cheng
, et al.
·
IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)
·
15
A Power-Saving Adaptive Equalizer With a Digital-Controlled Self-Slope Detection
2018
·
Yo-Hao Tu
, Kuo-Hsing Cheng
, et al.
·
IEEE Transactions on Circuits and Systems I Regular Papers
·
10
A Wide-Range All-Digital Delay-Locked Loop for Double Data Rate Synchronous Dynamic Random Access Memory Application
2018
·
Chih-Wei Tsai
, Yu-Ting Chiu
, et al.
·
IEEE International Symposium on Circuits and Systems proceedings
·
9
A 0.6-V 1.6-GHz 8-phase all digital PLL using multi-phase based TDC
2015
·
Yo-Hao Tu
, Jen-Chieh Liu
, et al.
·
IEICE Electronics Express
·
6
PDF
Low supply voltage and multiphase all‐digital crystal‐less clock generator
2018
·
Yo‐Hao Tu
, Jen‐Chieh Liu
, et al.
·
IET Circuits Devices & Systems
·
4
A body sensor node SoC for ECG/EMG applications with compressed sensing and wireless powering
2017
·
Yo-Hao Tu
, Kai-Wen Yao
, et al.
·
International Symposium on VLSI Design, Automation and Test
·
4
A 0.5-V all-digital clock-deskew buffer with I/Q phase outputs
2017
·
Yo-Hao Tu
, Jen-Chieh Liu
, et al.
·
Analog Integrated Circuits and Signal Processing
·
2
A digital crystal-less clock generator using a phase error corrector
2016
·
Jen-Chieh Liu
, Pei-Ying Lee
, et al.
·
Microsystem Technologies
·
2
A 3 GHz DLL-based clock generator with stuck locking protection
2010
·
Yo-Hao Tu
, Hsiang-Hao Chang
, et al.
·
IEEE International Conference on Electronics, Circuits and Systems (ICECS)
·
2
A chaotically injected timing technique for ring-based oscillators
2016
·
Yo-Hao Tu
, Kuo-Hsing Cheng
, et al.
·
IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)
·
1
A low supply voltage synchronous mirror delay with quadrature phase output
2014
·
Yo-Hao Tu
, Kuo-Hsing Cheng
, et al.
·
IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)
·
1
A 7.5-mW 10-Gb/s 16-QAM wireline transceiver with carrier synchronization and threshold calibration for mobile inter-chip communications in 16-nm FinFET
2019
·
Jieqiong Du
, Chien-Heng Wong
, et al.
·
IEEE/ACM International Symposium on Networks-on-Chip (NOCS)
PDF
應用於高速串列連結之關鍵技術設計與實現;Design and Implementation of Key Technologies Applied to High-Speed Serial Links
2018
·
涂祐豪
, Yo‐Hao Tu
Proportional Static-Phase-Error Reduction for Frequency-Multiplier-Based Delay-Locked-Loop Architecture
2016
·
Yo-Hao TU
, Jen-Chieh LIU
, et al.
·
IEICE Transactions on Electronics
A Synchronous Mirror Delay with Duty-Cycle Tunable Technology
2015
·
Yo-Hao Tu
, Kuo-Hsing Cheng
, et al.
·
IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)
具寬頻操作及自我相位校正之延遲鎖定迴路與頻率倍頻器 ; A Wide Range Delay-Locked Loop with Phase Error Calibration and Frequency Multiplier
2010
·
涂祐豪
, Yo‐Hao Tu
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Works count:
17
Citation count:
74
H-index:
5
I10-index:
3
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