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Mu-Shih Yeh

Performance of Stacked Nanosheets Gate-All-Around and Multi-Gate Thin-Film-Transistors
2018 · Yu-Ru Lin, Yi-Yun Yang, et al. · IEEE Journal of the Electron Devices Society · 30
Characterizing the Electrical Properties of a Novel Junctionless Poly-Si Ultrathin-Body Field-Effect Transistor Using a Trench Structure
2014 · Mu-Shih Yeh, Yung-Chun Wu, et al. · IEEE Electron Device Letters · 29
High Performance of Fin-Shaped Tunnel Field-Effect Transistor SONOS Nonvolatile Memory With All Programming Mechanisms in Single Device
2014 · Yi-Ruei Jhan, Yung-Chun Wu, et al. · IEEE Transactions on Electron Devices · 25
High performance ultra-thin body (2.4nm) poly-Si junctionless thin film transistors with a trench structure
2014 · Mu-Shih Yeh, Yung-Chun Wu, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 24
Low-Temperature Microwave Annealing for Tunnel Field-Effect Transistor
2014 · Yi-Ruei Jhan, Yung-Chun Wu, et al. · IEEE Electron Device Letters · 23
Ge FinFET CMOS Inverters With Improved Channel Surface Roughness by Using In-Situ ALD Digital O3 Treatment
2018 · M.-S. Yeh, G.-L. Luo, et al. · IEEE Journal of the Electron Devices Society · 19
Ge nanowire FETs with HfZrOx ferroelectric gate stack exhibiting SS of sub-60 mV/dec and biasing effects on ferroelectric reliability
2017 · C.-J. Su, T.-C. Hong, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 19
Junctionless Poly-Si Nanowire FET With Gated Raised S/D
2016 · Lun-Chun Chen, Mu-Shih Yeh, et al. · IEEE Journal of the Electron Devices Society · 19
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Fabrication, characterization and simulation of Ω-gate twin poly-Si FinFET nonvolatile memory
2013 · Mu-Shih Yeh, Yung-Chun Wu, et al. · Nanoscale Research Letters · 19
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Hot carrier degradation in novel strained-Si nMOSFETs
2004 · M.F. Lu, S. Chiang, et al. · IEEE International Reliability Physics Symposium proceedings · 19
High-Performance Gate-All-Around Poly-Si Thin-Film Transistors by Microwave Annealing With NH $_{\rm 3}$ Plasma Passivation
2013 · Mu-Shih Yeh, Yao-Jen Lee, et al. · IEEE Transactions on Nanotechnology · 18
A Comprehensive Study of Polymorphic Phase Distribution of Ferroelectric-Dielectrics and Interfacial Layer Effects on Negative Capacitance FETs for Sub-5 nm Node
2018 · Y.-T Tang, C.-J. Su, et al. · Symposium on VLSI Technology · 17
The physical analysis on electrical junction of junctionless FET
2017 · Lun-Chun Chen, Mu-Shih Yeh, et al. · AIP Advances · 16
Investigation of p-channel and n-channel junctionless gate-all-around polycrystalline silicon nanowires with silicon nanocrystals nonvolatile memory
2014 · Mu-Shih Yeh, Yung-Chun Wu, et al. · Applied Physics Letters · 8
Germanium Twin-Transistor Nonvolatile Memory With FinFET Structure
2020 · Siao-Cheng Yan, Chong-Jhe Sun, et al. · IEEE Journal of the Electron Devices Society · 7
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Low-Voltage Programmable Gate-All-Around (GAA) Nanosheet TFT Nonvolatile Memory Using Band-to-Band Tunneling Induced Hot Electron (BBHE) Method
2018 · Lun-Chun Chen, Hung-Bin Chen, et al. · IEEE Journal of the Electron Devices Society · 5
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Comprehensive Study of N-Channel and P-Channel Twin Poly-Si FinFET Nonvolatile Memory
2014 · Mu-Shih Yeh, Yung-Chun Wu, et al. · IEEE Transactions on Nanotechnology · 5
Band-to-Band Hot Hole Erase Mechanism of p-Channel Junctionless Silicon Nanowire Nonvolatile Memory
2015 · Yu-Hsien Lin, Mu-Shih Yeh, et al. · IEEE Transactions on Nanotechnology · 2
Study of Twin Ge FinFET Structure Non-Volatile Memory
2019 · Chien-Chang Li, Mu-Shih Yeh, et al. · Silicon Nanoelectronics Workshop (SNW) · 1
Fabrication and characterization of silicon nanowire ultra-thin channel poly-Si junctionless field effect transistors with a trench structure
2015 · Ko‐Wei Lin, Mu-Shih Yeh, et al. · IEEE Silicon Nanoelectronics Workshop · 1
A single poly-Si gate-all-around junctionless fin field-effect transistor for use in one-time programming nonvolatile memory
2014 · Mu-Shih Yeh, Yung-Chun Wu, et al. · Nanoscale Research Letters · 1
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Ge NW FETs Fabrication
2018 · Yao-Jen Lee Lee, Fu-Ju Hou, et al. · The Japan Society of Applied Physics
Comparison of Gate Structures of P-channel Poly-Si Nanowire Trench Ultra-thin Channel Juntionless Field-Effect Transistors
2015 · Y. C. Wu, K. W. Lin, et al. · International Conference on Solid State Devices and Materials (SSDM)
Enhanced Erasing Performance of Ω-Gate P-Channel Junctionless Fin-FET SOncOS Nonvolatile Memory
2014 · M.S. Yeh, Y.C. Wu, et al. · International Conference on Solid State Devices and Materials (SSDM)
Electrical Characteristics of Novel Junctionless FinFET Utilizing Trench Structure for Extreme Scaling
2014 · M.-S. Yeh, Y.-C. Wu, et al. · International Conference on Solid State Devices and Materials (SSDM)
Works count: 26
Citation count: 307
H-index: 13
I10-index: 13
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