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Author

Yogesh Shrivastava

ORCID: 0000-0002-0103-091X
Observed ORCID: 0000-0002-0103-091X
OpenAlex ID: A5029976749
Design of High-Speed Low Variation Static Noise Margin Ternary S-RAM Cells
2021 · Yogesh Shrivastava, Tarun Kumar Gupta · IEEE Transactions on Device and Materials Reliability · 32
Design of low‐power high‐speed CNFET 1‐trit unbalanced ternary multiplier
2019 · Yogesh Shrivastava, Tarun Kumar Gupta · International Journal of Numerical Modelling Electronic Networks Devices and Fields · 18
Design of Compact Reliable Energy Efficient Read Disturb Free 17T CNFET Ternary S-RAM Cell
2021 · Yogesh Shrivastava, Tarun Kumar Gupta · IEEE Transactions on Device and Materials Reliability · 15
Designing of Low-Power High-Speed Noise Immune CNTFET 1-Trit Unbalanced Ternary Subtractor
2021 · Yogesh Shrivastava, Tarun Kumar Gupta · Journal of Circuits Systems and Computers · 8
Efficient Noise Immune Robust Ternary Subtractor Designs*
2023 · Yogesh Shrivastava, Tarun Kumar Gupta · Lecture notes in networks and systems · 1
Design of Efficient Ternary Subtractor
2020 · Yogesh Shrivastava, Tarun Kumar Gupta · Lecture notes in electrical engineering
Methods to design ternary gates and adders
2019 · Yogesh Shrivastava, Tarun Gupta · Institution of Engineering and Technology eBooks
Works count: 7
Citation count: 74
H-index: 4
I10-index: 3
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