Get started
Author

Hsien-Ching Lo

Observed names: H. C. Lo, H.-C. Lo, H.C. Lo
ORCID: 0000-0003-0448-0614
Observed ORCID: 0000-0003-0448-0614
OpenAlex ID: A5030464470
A 12nm FinFET Technology Featuring 2nd Generation FinFET for Low Power and High Performance Applications
2018 · H.C. Lo, D. Choi, et al. · Symposium on VLSI Technology · 18
Effects of high in-situ source/drain boron doping in p-FinFETs on physical and device performance characteristics
2018 · Shashidhar Shintri, Chloe Yong, et al. · Materials Science in Semiconductor Processing · 18
Source/drain eSiGe engineering for FinFET technology
2017 · Jianwei Peng, Yi Qi, et al. · Semiconductor Science and Technology · 18
PDF
Abnormal Silicon-Germanium (SiGe) Epitaxial Growth in FinFETs
2020 · Talapady Srivatsa Bhat, Shashidhar Shintri, et al. · IEEE Transactions on Semiconductor Manufacturing · 16
In-Situ Boron Doped SiGe Epitaxy Optimization for FinFET Source/Drain
2016 · Yi Qi, Jianwei Peng, et al. · ECS Transactions · 15
45nm SOI CMOS Technology with 3X hole mobility enhancement and Asymmetric transistor for high performance CPU application
2007 · Samuel K.H. Fung, H.C. Lo, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 11
BEOL process integration of 65nm Cu/low k interconnects
2004 · C.C. Jeng, W.K. Wan, et al. · IEEE International Interconnect Technology Conference (IITC) · 6
Wafer Level Variability Improvement by Spatial Source/Drain Activation and Ion Implantation Super Scan for FinFET Technology
2018 · Yanzhen Wang, Yoong Hooi Yong, et al. · IEEE Transactions on Semiconductor Manufacturing · 5
Trade-Off between Gate Oxide Integrity and Transistor Performance for FinFET Technology
2017 · Hsien-Ching Lo, Jianwei Peng, et al. · ECS Journal of Solid State Science and Technology · 5
PDF
14nm FinFET technology SRAM cell margin evaluation and analysis by local layout effect
2017 · S. Y. Mun, D. Burnett, et al. · IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference · 4
CMOS on dual SOI thickness for optimal performance
2010 · H.C. Lo, C.T. Li, et al. · Microelectronic Engineering · 4
A Novel Approach to Control Source/Drain Cavity Profile for Device Performance Improvement
2018 · Hsien-Ching Lo, Jianwei Peng, et al. · IEEE Transactions on Electron Devices · 3
Dual-curvature cavity for improved p-type FinFET performance
2018 · Jianwei Peng, Hsien-Ching Lo, et al. · Semiconductor Science and Technology · 3
PDF
Optimization of Back Channel Leakage Characteristic in PD SOI p-MOSFET
2010 · H. C. Lo, Y. T. Chen, et al. · Journal of The Electrochemical Society · 3
Performance boost using spacer-confined cavity for advanced FinFET technology
2018 · Hsien-Ching Lo, Jianwei Peng, et al. · Semiconductor Science and Technology · 1
14nm FinFET Device Boost via 2nd Generation Fins Optimized for High Performance CMOS Applications
2018 · E. M. Bazizi, E. K. Banghart, et al. · International Conference on Simulation of Semiconductor Processes and Devices · 1
In-Situ Boron Doped SiGe Epitaxy Optimization for FinFET Source/Drain
2016 · Yi Qi, Jianwei Peng, et al. · ECS Meeting Abstracts · 1
Sub-20nm Device Voltage-Sensitive SRAM Characterization and Failure Analysis
2018 · Seng Nguon Ting, Hsien-Ching Lo, et al. · Proceedings - International Symposium for Testing and Failure Analysis
Transistor Optimization with Novel Cavity for Advanced FinFET Technology
2018 · Hsien-Ching Lo, Jianwei Peng, et al. · International Conference on Simulation of Semiconductor Processes and Devices
The Characteristics and Control of Body-to-Body Leakage Current in PD-SOI
2009 · H. C. Lo, W. C. Luo, et al. · Journal of The Electrochemical Society
PD-SOI MOSFET Body-to-Body leakage scaling trend and optimization
2008 · H.C. Lo, W.C. Luo, et al. · IEEE International SOI Conference (SOI)
Works count: 21
Citation count: 132
H-index: 6
I10-index: 6
Year
Topic
Type