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Y.H. Chen

Observed names: Y. H. Chen, Yong-Si Chen, Yun-Fan Chen
ORCID: 0009-0001-4233-4354
Observed ORCID: 0009-0001-4233-4354
OpenAlex ID: A5031869799
A 16nm FinFET CMOS technology for mobile SoC and computing applications
2013 · Shien-Yang Wu, C. Y. Lin, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 150
A 45nm dual-port SRAM with write and read capability enhancement at low voltage
2007 · D.P. Wang, H.J. Liao, et al. · IEEE International SOC Conference (SOCC) · 71
Ultra High Density SoIC with Sub-micron Bond Pitch
2020 · Y. H. Chen, C. A. Yang, et al. · 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) · 69
A 0.6V 45nm adaptive dual-rail SRAM compiler circuit design for lower VDD_min VLSIs
2008 · Y.H. Chen, W.M. Chan, et al. · IEEE Symposium on VLSI Circuits (VLSI-Circuits) · 42
An implementation of positioning system in indoor environment based on active RFID
2009 · Ching-Sheng Wang, Chun-Hong Huang, et al. · Joint Conferences on Pervasive Computing · 23
A full Cu damascene metallization process for sub-0.18 /spl mu/m RF CMOS SoC high Q inductor and MIM capacitor application at 2.4 GHz and 5.3 GHz
2001 · C.C. Lin, H.M. Hsu, et al. · IEEE International Interconnect Technology Conference (IITC) · 22
High-aspect ratio through silicon via (TSV) technology
2012 · H.B. Chang, H.Y. Chen, et al. · Symposium on VLSI Technology · 18
An ultra-thin interposer utilizing 3D TSV technology
2012 · W.C. Chiou, K.F. Yang, et al. · Symposium on VLSI Technology · 16
Yield and reliability of 3DIC technology for advanced 28nm node and beyond
2011 · K.F. Yang, Ting Wu, et al. · Symposium on VLSI Technology · 9
Assessment on Nanosheet Transistor Variants Beyond 2nm Node
2025 · Chih-Hao Chang, P.C. Shen, et al. · 5
90 nm generation Cu/CVD low-k (k>2.5) interconnect technology
2003 · T.I. Bao, C.C. Ko, et al. · 5
On Cyber-Physical Fault Resilience in Data Communication: A Case From A LoRaWAN Network Systems Design
2024 · Chao Wang, Cheng-Hsun Chuang, et al. · ACM Transactions on Cyber-Physical Systems · 4
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An integrated air gap structure to achieve high-performance TSV interconnects for 28nm 3D-IC integration
2013 · E.B. Liao, Kai-Yu Cheng, et al. · Symposium on VLSI Technology · 3
Electrochemically induced defects during post Cu CMP cleaning
2004 · W.C. Chiou, Y.H. Chen, et al. · IEEE International Interconnect Technology Conference (IITC) · 3
Novel CMP Barrier Slurry for Integrated Porous Low-k Technology of 45nm Node
2006 · H.H. Kuo, J.Y. Song, et al. · International Interconnect Technology Conference · 1
Advanced Cu/low-k (k=2.2) multilevel interconnect for 0.10/0.07 μm generation
2003 · S.M. Jang, Y.H. Chen, et al. · Symposium on VLSI Technology · 1
Towards An Indoor Daylight-Guiding System
2026 · Jhong-Sian He, Yun-Fan Chen, et al. · Mediterranean Conference on Embedded Computing (MECO)
Hot-Spot Thermal Sensor Design in FinFETs
2019 · S. L. Liu, J. J. Horng, et al. · Technical digest - International Electron Devices Meeting/Technical digest
People productivity improvement via cloud machine monitor
2014 · Y. H. Chen, C. J. Huang, et al. · Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)
Breakthrough of 6% people productivity improvement via the development of Cloud Monitor
2013 · Y.H. Chen, C.J. Huang, et al.
Novel CMP slurries for planarization of multilevel copper interconnect
2004 · J.Y. Song, Y.H. Chen, et al. · Symposium on VLSI Technology
Works count: 21
Citation count: 442
H-index: 9
I10-index: 8
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